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參數(shù)資料
| 型號： | MRF275G |
| 元件分類： | 功率晶體管 |
| 英文描述： | 2 CHANNEL, UHF BAND, Si, N-CHANNEL, RF POWER, MOSFET |
| 封裝： | CASE 375-04, 4 PIN |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 262K |
| 代理商： | MRF275G |
Figure 16. MRF275G Test Fixture
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure deter-
mines the capacitors from gate–to–drain (Cgd), and gate–to–
source (Cgs). The PN junction formed during the fabrication
of the MOSFET results in a junction capacitance from drain–
to–source (Cds).
These capacitances are characterized as input (Ciss), out-
put (Coss) and reverse transfer (Crss) capacitances on data
sheets. The relationships between the inter–terminal capaci-
tances and those given on data sheets are shown below. The
Ciss can be specified in two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operat-
ing conditions in RF applications.
Cgd
GA TE
SOURCE
Cgs
DRAIN
Cds
Ciss = Cgd + Cgs
Coss = Cgd + Cds
Crss = Cgd
The Ciss given in the electrical characteristics table was
measured using method 2 above. It should be noted that
Ciss, Coss, Crss are measured at zero drain current and are
provided for general information about the device. They are
not RF design parameters and no attempt should be made to
use them as such.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, VDS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, VDS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the MOSFET is a polysilicon material, and is
electrically isolated from the source by a layer of oxide. The
input resistance is very high — on the order of 109 ohms —
resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
VGS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating (or any of the maximum ratings on the front page). Ex-
ceeding the rated VGS can result in permanent damage to
the oxide layer in the gate region.
Gate Termination — The gates of this device are essen-
tially capacitors. Circuits that leave the gate open–circuited
or floating should be avoided. These conditions can result in
turn–on of the devices due to voltage build–up on the input
capacitor due to leakage currents or pickup.
Gate Protection — These devices do not have an internal
monolithic zener diode from gate–to–source. If gate protec-
tion is required, an external zener diode is recommended.
Using a resistor to keep the gate–to–source impedance
low also helps damp transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
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