
Mobile Low-Power DDR SDRAM
MT46H64M16LF – 16 Meg x 16 x 4 Banks
MT46H32M32LF – 8 Meg x 32 x 4 Banks
Features
VDD/VDDQ = 1.70–1.95V
Bidirectional data strobe per byte of data (DQS)
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
4 internal banks for concurrent operation
Data masks (DM) for masking write data—one mask
per byte
Programmable burst lengths (BL): 2, 4, 8, or
161 Concurrent auto precharge option is supported
Auto refresh and self refresh modes
1.8V LVCMOS-compatible inputs
On-chip temp sensor to control self refresh rate
Partial-array self refresh (PASR)
Deep power-down (DPD)
Status read register (SRR)
Selectable output drive strength (DS)
Clock stop capability
64ms refresh
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
Clock Rate (MHz)
Access Time
-5
200
5.0ns
-54
185
5.0ns
-6
166
5.5ns
-75
133
6.0ns
Options
Marking
VDD/VDDQ
– 1.8V/1.8V
H
Configuration
– 64 Meg x 16 (16 Meg x 16 x 4 banks)
64M16
– 32 Meg x 32 (8 Meg x 32 x 4 banks)
32M32
Row-size option
– JEDEC-standard option
LF
LG
Plastic green package
CK
– 90-ball VFBGA (10mm x
13mm)3CM
Timing – cycle time
– 5ns @ CL = 3
-5
– 5.4ns @ CL = 3
-54
– 6ns @ CL = 3
-6
– 7.5ns @ CL = 3
-75
Power
– Standard IDD2/IDD6
None
– Low-power IDD2/IDD6
L
Operating temperature range
– Commercial (0 to +70C)
None
– Industrial (–40C to +85C)
IT
Design revision
:A
Notes: 1. Contact factory for availability.
2. Only available for x16 configuration.
3. Only available for x32 configuration.
1Gb: x16, x32 Mobile LPDDR SDRAM
Features
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. K 07/09 EN
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2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.