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參數資料
| 型號： | MTD2955V |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | P-Channel Enhancement Mode Field Effect Transistor |
| 中文描述： | 12 A, 60 V, 0.23 ohm, P-CHANNEL, Si, POWER, MOSFET, TO-252 |
| 封裝： | DPAK-3 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 148K |
| 代理商： | MTD2955V |
1
Motorola, Inc. 1997
P–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M
)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage
— Non–repetitive (tp
≤
10 ms)
Drain Current — Continuous
Drain Current
— Continuous @ 100
°
C
Drain Current
— Single Pulse (tp
≤
10
μ
s)
Total Power Dissipation
Derate above 25
°
C
Total Power Dissipation @ 25
°
C(1)
60
Vdc
±
15
±
25
Vdc
Vpk
12
8.0
42
Adc
Apk
60
0.4
2.1
Watts
W/
°
C
Watts
Operating and Storage Temperature Range
TJ, Tstg
EAS
–55 to 175
°
C
mJ
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25
)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient(1)
216
R
θ
JC
R
θ
JA
R
θ
JA
TL
2.5
100
71.4
°
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
260
°
C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 3
Order this document
by MTD2955V/D
SEMICONDUCTOR TECHNICAL DATA
TM
CASE 369A–13, Style 2
DPAK Surface Mount
TMOS POWER FET
12 AMPERES
60 VOLTS
RDS(on) = 0.230 OHM
D
S
G
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