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參數(shù)資料
型號: MTD6N20E
廠商: MOTOROLA INC
元件分類: JFETs
英文描述: TMOS POWER FET 6.0 AMPERES 200 VOLTS RDS(on) = 0.7 OHM
中文描述: 6 A, 200 V, 0.7 ohm, N-CHANNEL, Si, POWER, MOSFET
文件頁數(shù): 1/10頁
文件大小: 269K
代理商: MTD6N20E
1
Motorola, Inc. 1995
!
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add –T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
VDGR
VGS
VGSM
200
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M
)
Gate–to–Source Voltage — Continuous
200
Vdc
— Non–repetitive (tp
10 ms)
±
20
±
40
Vdc
Vpk
Drain Current
— Continuous
— Continuous @ 100
°
C
— Single Pulse (tp
10
μ
s)
ID
ID
IDM
6.0
3.8
18
Adc
Apk
Total Power Dissipation
Derate above 25
°
C
Total Power Dissipation @ TA = 25
°
C, when mounted to minimum recommended pad size
PD
50
0.4
1.75
Watts
W/
°
C
Watts
Operating and Storage Temperature Range
TJ, Tstg
EAS
–55 to 150
°
C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG = 25
)
54
mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
— Junction to Ambient, when mounted to minimum recommended pad size
R
θ
JC
R
θ
JA
R
θ
JA
TL
2.50
100
71.4
°
C/W
Maximum Temperature for Soldering Purposes, 1/8
from case for 10 seconds
260
°
C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTD6N20E/D
SEMICONDUCTOR TECHNICAL DATA
D
S
G
CASE 369A–13, Style 2
DPAK
TMOS POWER FET
6.0 AMPERES
200 VOLTS
RDS(on) = 0.7 OHM
Motorola Preferred Device
相關PDF資料
PDF描述
MTD6P10E TMOS POWER FET 6.0 AMPERES 100 VOLTS RDS(on) = 0.66 OHM
MTM55N10 N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR
MTM60N06 N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR
MTP1302 TMOS POWER FET 42 AMPERES 30 VOLTS RDS(on) = 22 mohm
MTP1306 TMOS POWER FET 75 AMPERES 30 VOLTS RDS(on) = 0.0065 OHM
相關代理商/技術參數(shù)
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