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參數資料
| 型號： | MX812J |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | VSR CODEC WITH DRAM CONTROL |
| 中文描述： | 振動時效編解碼器DRAM的控制 |
| 文件頁數： | 13/13頁 |
| 文件大小： | 115K |
| 代理商： | MX812J |
VSR CODEC with DRAM CONTROL
13
MX812 PRELIMINARY INFORMATION
1997 MX
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
All trademarks and service marks are held by their respective companies.
Package Outline
Figure 11 shows the MX812J Ceramic Dual In-Line, or Cerdip, Package. The MX812DW is
shown in Figure 12. Pin 1 is marked with an indent spot on each chip. Pins number counter-
clockwise when viewed from the top side.
Handling Precautions
The MX812 is a CMOS LSI circuit which includes input protection. However, precautions should
be taken to prevent static discharges which may cause damage.
Figure 11 - MX812J 28-pin Cerdip
Figure 12 - MX812DW SOIC-28 Package
R
P
J
K
M
L
N
A
B
F
G
E
C
H
D
Pin 1
Dimension
in,(mm)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Min.
0.698 (17.72)
0.291 (7.39)
0.092 (2.33)
0.004 (0.102)
0.014 (0.36)
0.050 (1.27)
0.026 (0.66)
0.096 (2.43)
5
0.020 (0.51)
0.025 (0.63)
0.041 (1.04)
0.009 (0.23)
5
0.39 (9.91)
Max.
0.706 (17.97)
0.299 (7.59)
typical
0.012 (0.304)
0.018 (0.46)
typical
typical
0.104 (2.64)
typical
0.040 (1.02)
typical
typical
0.011 (0.28)
typical
0.414 (10.51)
Package Tolerances
A
B
E
F
G
C
D
H
Dimension
in,(mm)
A
B
C
D
E
F
G
H
J
K
L
Min.
1.44 (36.58)
0.51 (13.06)
0.18 (4.49)
0.12 (3.0)
0.10 (2.54)
0.018 (0.45)
0.055 (1.39)
0.02 (.50)
0.61 (15.50)
0.670 (17.0)
0.009 (0.25)
Max.
1.46 (37.05)
0.53 (13.36)
0.220 (5.57)
0.15 (3.81)
typical
typical
typical
0.05 (1.30)
0.62 (15.70)
typical
typical
J
K
L
Pin 1
Package Tolerances
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