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參數(shù)資料
| 型號(hào)： | MX812J |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | VSR CODEC WITH DRAM CONTROL |
| 中文描述： | 振動(dòng)時(shí)效編解碼器DRAM的控制 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大小： | 115K |
| 代理商： | MX812J |
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VSR CODEC with DRAM CONTROL
8
MX812 PRELIMINARY INFORMATION
1997 MX
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
All trademarks and service marks are held by their respective companies.
Figure 8 - Typical Command Sequences
Figure 7 - Control Timing Relationships
Figure 6 - Control Timing Information
Control Timing Information
Figure 6 shows the timing parameters for two-way communication between the
μ
Controller and Cellular peripherals on the
“C-BUS.” Figure 7 shows the timing relationships between the Serial Clock and Data.
CHIP
SELECT
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
ADDRESS/COMMAND
BYTE
FIRST
DATA
BYTE
LAST
DATA
BYTE
FIRST
REPLY
DATA
BYTE
LAST
REPLY
DATA
BYTE
Logic
level
is
not
important
MSB
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
t
t
t
CSOFF
t
CSH
HIZ
t
NXT
t
NXT
CK
t
CSE
t
t
t
t
t
t
t
CH
CK
CDH
RDH
RDS
CDS
CL
70% VDD
30% VDD
COMMAND DATA
(from C)
SERIAL CLOCK
(from C)
REPLY DATA
(to C)
I bit (idle)
Device Condition
MT bit Command
Buffer Status
IF bit (Flag)
Interrupt
(IRQ) Output
New 'Store, Play or Wait'
Command from C-BUS
C1
C2
C3
Read Status Register
**
** The value read from the Status Register at these times will include a valid 'Power' reading if the Codec is set to the Encode mode.
C1
C2
C3
Command Executing
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