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參數資料
| 型號： | P89C669 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-bit microcontroller family with extended memory 96 kB Flash with 2 kB RAM |
| 中文描述： | 80C51的8位擴展內存，2 KB RAM內存96 kB閃存微控制器系列 |
| 文件頁數： | 16/33頁 |
| 文件大小： | 827K |
| 代理商： | P89C669 |
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Special function registers
…continued
Description
SFR
addr.
MSB
P
P
8
9
P
R
1
[1]
[2]
[3]
[4]
[5]
[6]
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
Extended SFRs accessed by preceding the instruction with MX escape (opcode A5h).
Power-on reset is 10H. Other reset is 00H.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any of them is written if BRGEN = 1, result is unpredictable.
The unimplemented bits (labeled ‘-’) in the SFRs are X’s (unknown) at all times. ‘1’s should NOT be written to these bits, as they may be used for other purposes in future
derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.
S1ADEN
[2]
S1STAT
[2]
SP
Serial Port 1 Address Enable
Serial Port 1 Status
Stack Pointer (Stack Pointer
LOW Byte)
Stack Pointer HIGH
83H
[3]
84H
[3]
81H
00H
00H
[6]
07H
DBMOD_1
INTLO_1
CIDIS_1
DBISEL1
FE_1
BR_1
OE_1
STINT_1
SPE
[2]
FBH
[3]
00H
Bit address 8F
88H
8E
TR1
CE
EXF2
-
8D
TF0
CD
RCLK
-
8C
TR0
CC
TCLK
-
8B
IE1
CB
EXEN2
-
8A
IT1
CA
TR2
-
89
IE0
C9
C/T2
T2OE
88
IT0
C8
CP/RL2
DCEN
TCON
[1]
Timer Control Register
TF1
CF
TF2
-
00H
T2CON
[1][2]
T2MOD
[2]
TH0
TH1
TH2
TL0
TL1
TL2
TMOD
WDTRST
[2]
WDCON
[2]
Timer2 Control Register
Timer2 Mode Control
Timer 0 HIGH
Timer 1 HIGH
Timer 2 HIGH
Timer 0 LOW
Timer 1 LOW
Timer 2 LOW
Timer 0 and 1 Mode
Watchdog Timer Reset
Watchdog Timer Control
C8H
C9H
8CH
8DH
CDH
8AH
8BH
CCH
89H
A6H
8FH
[3]
00H
00H
[6]
00H
00H
00H
00H
00H
00H
00H
FFH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
-
-
-
-
-
WDPRE2 WDPRE1 WDPRE0 00H
[6]
Table 5:
Name
Bit functions and addresses
Reset
value
LSB
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