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參數資料
| 型號： | P89C669 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 8-bit microcontroller family with extended memory 96 kB Flash with 2 kB RAM |
| 中文描述： | 80C51的8位擴展內存，2 KB RAM內存96 kB閃存微控制器系列 |
| 文件頁數： | 19/33頁 |
| 文件大?。?/td> | 827K |
| 代理商： | P89C669 |
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Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
Product data
Rev. 02 — 13 November 2003
19 of 33
9397 750 12299
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
c) Maximum total I
OL
for all outputs: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
[10] Pin capacitance is characterized but not tested.
[9]
10. Dynamic characteristics
Table 9:
T
amb
= 0
°
C to +70
°
C for commercial unless otherwise specified. Formulae including t
CLCL
assume oscillator signal with
50/50 duty cycle.
[1][2][3]
Symbol
Figure
Parameter
AC electrical characteristics
4.5 V < V
DD
< 5.5 V
Variable clock
[4]
Min
0
-
t
CLCL
15
0.5t
CLCL
15
0.5t
CLCL
15
-
0.5t
CLCL
12
1.5t
CLCL
20
-
0
-
-
Unit
f
OSC
= 24 MHz
[4]
Min
Max
24
-
-
-
-
2t
CLCL
30
-
-
1.5t
CLCL
35
-
0.5t
CLCL
5
2.5t
CLCL
30
Max
-
-
-
-
-
53
-
-
27
-
15
74
f
OSC
t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
5
5
5
5
,
6
,
7
5
,
6
,
7
5
5
5
5
5
5
5
Oscillator frequency
Clock cycle
ALE pulse width
Address valid to ALE LOW
Address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
(non-Extended Addressing Mode)
Address (A16-A22) to valid instruction
in (Extended Addressing Mode)
PSEN LOW to address float
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41.5
26
5
5
8
42
0
-
-
t
AVIV1
5
-
1.5t
CLCL
34
-
28
ns
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
5
-
8
-
8
ns
6
7
6
6
6
6
6
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in (non-Extended
Addressing Mode)
Address (A16-A22) to valid data in
(Extended Addressing Mode)
ALE LOW to RD or WR LOW
Address valid to WR or RD LOW
(non-Extended Addressing Mode)
Address (A16-A22) valid to WR or RD
LOW (Extended Addressing Mode)
3t
CLCL
20
3t
CLCL
20
-
0
-
-
-
-
-
2.5t
CLCL
40
-
t
CLCL
15
4t
CLCL
35
4.5t
CLCL
30
105
105
-
0
-
-
-
-
-
64
-
26
131
157
ns
ns
ns
ns
ns
ns
ns
t
AVDV1
6
-
3.5t
CLCL
35
-
110
ns
t
LLWL
t
AVWL
6
,
7
6
,
7
1.5t
CLCL
10
2t
CLCL
5
1.5t
CLCL
+ 20
-
52
78
82
-
ns
ns
t
AVWL1
6
,
7
t
CLCL
10
-
31
-
ns
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