- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382379 > PCD3316 (NXP Semiconductors N.V.) Caller-ID on Call Waiting CIDCW receiver PDF資料下載
參數(shù)資料
| 型號： | PCD3316 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Caller-ID on Call Waiting CIDCW receiver |
| 中文描述： | 來電呼叫等待CIDCW編號接收機 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大小： | 534K |
| 代理商： | PCD3316 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
Philips Semiconductors
PCD3316
CIDCW receiver
Product specification
11 March 1999
11 of 30
9397 750 04824
Philips Electronics N.V. 1999. All rights reserved.
Unetited
7.12.2
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition
(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a
STOP condition (P); see
Figure 10
.
7.12.3
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal; see
Figure 11
.
7.12.4
Acknowledge
The number of data bytes transferred between the START and the STOP conditions
from the transmitter to the receiver is unlimited. Each byte of eight bits is followed by
an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge-related
clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the slave transmitter.
Fig 9.
I
2
C-bus configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
Fig 10. START and STOP conditions for the I
2
C-bus.
MBA608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig 11. I
2
C-bus bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD3316T | Caller-ID on Call Waiting CIDCW receiver |
| PCD3330-1 | Multistandard repertory dialler/ringer with EEPROM |
| PCD3330-1P | Multistandard repertory dialler/ringer with EEPROM |
| PCD3330-1T | Multistandard repertory dialler/ringer with EEPROM |
| PCD3354AH | 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD3316T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Caller-ID on Call Waiting CIDCW receiver |
| PCD3316TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Caller Number ID Circuit |
| PCD3320CD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pulse Telephone Dialer |
| PCD3321CD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pulse Telephone Dialer |
| PCD3322CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pulse Telephone Dialer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。