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| 型號(hào)： | PCD3316 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Caller-ID on Call Waiting CIDCW receiver |
| 中文描述： | 來(lái)電呼叫等待CIDCW編號(hào)接收機(jī) |
| 文件頁(yè)數(shù)： | 20/30頁(yè) |
| 文件大?。?/td> | 534K |
| 代理商： | PCD3316 |
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Philips Semiconductors
PCD3316
CIDCW receiver
Product specification
11 March 1999
20 of 30
9397 750 04824
Philips Electronics N.V. 1999. All rights reserved.
GND < V
I
< V
DD
. The leakage currents are generally very small, <1 nA. The value given here, 1
μ
A, is a maximum that can occur after
an Electrostatic Stress on the pin.
When FSK is selected the signal power is measured between 1000 and 2200 Hz. When CAS is selected signal levels are measured
between 2000 and 2800 Hz.
The IRQ pin is implemented as a 3-state pin which is only active (either HIGH or LOW) when an interrupt occurs. A pull-up or pull-down
has to be connected to define the line when no interrupt is generated.
Verified on sampling basis.
According to Bellcore specification: near end speech level
≤
7 dBm ASL (ASL = Active Speech Level), referenced to 600
, according
to method B of recommendation P.56.
[10] Pins SCL and SDA are equipped with an open-drain output buffer. The pins have no clamp diode to V
DD
.
[11] The input threshold voltage of SCL and SDA meet the I
2
C-bus specification. Therefore, an input voltage below 0.3V
DD
will be recognized
as a logic 0 and an input voltage above 0.7V
DD
will be recognized as a logic 1
[12] Maximum capacitive load for each bus line is 400 pF.
[13] C1
i
and C2
i
are the total internal capacitances (including gate capacitance and leadframe capacitance).
[1]
Except for FSK and CAS detection, all circuitry works already when V
DD
> V
POR(H)
. Since the I
2
C-bus interface will work (starts to
acknowledge), the application can start reading the LOW-BAT Indication bit (Status register, bit 5) to check whether the supply voltage
has reached the operating voltage level. A voltage divider network can be connected to pins V
DD
, LOWBAT and AGND/DGND such that
V
LOWBAT
= V
ref
if V
DD
= V
DD(min)
.
The power-on reset LOW level is defined as V
POR(L)
= V
POR(H)
V
hys(POR)
. By design V
POR(L)
is always lower than V
POR(H)
.
32 kHz oscillator on (MIN Interrupt, SEC Interrupt, Polarity change, Low battery and Level detect available).
3.58 MHz oscillator on (device fully operational).
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
3.58 MHz oscillator (pins HXIN and HXOUT)
V
HXIN(p-p)
external clock signal amplitude
(peak-to-peak value) on pin HXIN
Z
i(HXIN)
input impedance on pin HXIN
C1
i
; C2
i
input capacitance on pins HXIN and
HXOUT
[13]
32 kHz oscillator (pins LXIN and LXOUT)
g
m
transconductance
C
i(LXIN)
LXIN input capacitance
C
o(LXOUT)
LXOUT output capacitance
0.5
V
DD
V
300
1000
10
k
pF
V
i(p-p)
< 50 mV
2
4
13
10
10
μ
S
pF
pF
Table 18: Characteristics
…continued
V
DD
= 2.5 to 3.6 V; T
amb
=
25 to +70
°
C; HXIN = 3.579545 MHz
±
0.05%; LXIN = 32.768 kHz
±
0.1%; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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