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參數資料
| 型號： | PCD3316 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Caller-ID on Call Waiting CIDCW receiver |
| 中文描述： | 來電呼叫等待CIDCW編號接收機 |
| 文件頁數： | 14/30頁 |
| 文件大小： | 534K |
| 代理商： | PCD3316 |
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Philips Semiconductors
PCD3316
CIDCW receiver
Product specification
11 March 1999
14 of 30
9397 750 04824
Philips Electronics N.V. 1999. All rights reserved.
Unetited
7.12.6
I
2
C-bus bit rate
When a microcontroller is used that implements an I
2
C-bus in software, the bit rate of
the I
2
C-bus can be critical during reception of FSK. The collection of the interrupt
data and FSK-data from the PCD3316 takes 48 bits on the I
2
C-bus. With an FSK
baud rate of 1200 (corresponds to 1200 bits per second) the minimal speed of the
I
2
C-bus should be 5.76 kbits/s. Additional interrupts generated by the time base of the
PCD3316 will cause the processor to collect extra information from the PCD3316.
As a consequence, the FSK-data can be overrun in the PCD3316 and one data byte
will be lost. In this case, the time base interrupt should be suppressed while FSK is
active. This can be done by setting the ‘INT-SUP on/off’ bit (bit 4 in Mode register 2).
The ‘TB on/off’ bit (bit 6 in Mode register 2) will still be set but the IRQ output will not
be activated by the time base interrupt. Any time base interrupt can be detected by
the microcontroller when an FSK interrupt is processed by reading the Interrupt
register.
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