
1998 Jun 17
16
Philips Semiconductors
Product specification
FLEX
Pager Decoder
PCD5008
8.4.3
C
ONFIGURATION SEQUENCE
A typical configuration and synchronisation sequence
would be as follows, see Fig.11 for event timings:
1.
The PCD5008 is reset by the host.
2.
After 1 second the PCD5008 interrupts the host to
read the part ID by pulling the READY line LOW.
3.
The host pulls SS LOW at the start of each
SPI transfer and clocks out the part ID data.
4.
The host configures the following aspects of PCD5008
operation:
a) General configuration (Section 8.4.4)
b) Receiver operation (Section 8.5)
c) FLEX
CAPCODE configuration (Section 8.6).
The PCD5008 writes a part ID packet in response to
each incoming packet.
5.
At the end of each packet the PCD5008 pulls the
READY line HIGH, and then LOW again to indicate
that packet processing is complete.
The host writes a control packet to enable FLEX
decoding in the PCD5008 (Section 8.4.7).
The host writes a checksum packet to enable SPI data
output by the PCD5008 (Section 8.4.2).
On recognising a SYNC word, the PCD5008
synchronises to the channel.
The PCD5008 initiates an SPI transfer writing the
status packet, indicating that it is now in synchronous
mode.
6.
7.
8.
9.
Fig.11 Typical configuration and synchronisation sequence.
handbook, full pagewidth
MBK097
SPI
DECODER-TO-HOST
RESET
READY
SS
FLEX DATASTREAM
SPI
HOST-TO-DECODER
checksum packet
(7)
control packet
(6)
partid packet
(4)
configuration packets
(addresses, receiver etc.)
status packet
(9)
partid packet
(4)
(1)
(2)
(3)
(5)
(5)
(5)
(8)
SYNC
Numbers within parenthesis refer to sequence numbers, see Section 8.4.3.