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參數資料
| 型號： | PCD5008 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | FLEX Pager Decoder |
| 中文描述： | FleX創建傳呼機解碼器 |
| 文件頁數： | 7/64頁 |
| 文件大小： | 341K |
| 代理商： | PCD5008 |
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1998 Jun 17
7
Philips Semiconductors
Product specification
FLEX
Pager Decoder
PCD5008
The PCD5008 interfaces to a host through a serial
peripheral interface (SPI). The host can then interpret the
message information in an appropriate manner (numeric,
alphanumeric, binary, etc.). This function is provided by
the FLEXstack
software.
The PCD5008 enables the host to operate in a low power
mode when no message information for the paging device
is being received. It has a 38.4 kHz clock output capable
of driving other devices, and has a 1-minute timer that
offers low-power support for a real-time clock function on
the host. The host can use receiver control lines which are
not required by the receiver as expansion ports to control
other peripheral devices.
8.2
Clocking, reset and start-up
8.2.1
O
SCILLATOR
The PCD5008 uses an inverting crystal oscillator.
The clock signal for the internal circuitry is derived via an
amplifier from the oscillator input pin EXTAL. Alternatively,
an external clock signal can be fed in at input pin EXTAL.
In this case the internal oscillator can be disabled by
pulling the OSCPD input pin HIGH.This reduces current
consumption and routes EXTAL directly to the internal
clock signal. When using a crystal, an external feedback
resistor and the load capacitances need to be connected
to pins EXTAL and XTAL (Fig.18). See Section 12 for the
recommended crystal parameters and the specification of
the oscillator transconductance to guarantee correct
start-up.
8.2.2
R
ESET AND START
-
UP CONDITIONS
The PCD5008 is reset by pulling the RESET input LOW.
After releasing the RESET by pulling it HIGH, the
PCD5008 counts 76800 clock cycles (typically 1 second)
before pulling READY LOW to indicate that the decoder is
ready for configuration via the SPI.
See Fig.3 and Section 11 for the PCD5008 timing
specifications when power is applied.
See Fig.4 and Section 11 for the PCD5008 timing
specifications when it is reset.
Fig.3 Start-up timing.
handbook, full pagewidth
MBK031
th(rst)
tWUL(osc-READY)
tHL(RESET-READY)
tstrt(osc)
VDD
oscillator
RESET
READY
相關PDF資料 |
PDF描述 |
|---|---|
| PCD5008H | FLEX Pager Decoder |
| PCD5013 | FLEX roaming decoder II |
| PCD5013H | FLEX roaming decoder II |
| PCD5032 | ADPCM CODEC for digital cordless telephones |
| PCD5032H | ADPCM CODEC for digital cordless telephones |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCD5008H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
| PCD5008HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5013 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX roaming decoder II |
| PCD5013H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX roaming decoder II |
| PCD5032 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ADPCM CODEC for digital cordless telephones |
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