欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: PLSI1016-80LT
英文描述: Electrically-Erasable Complex PLD
中文描述: 電可擦除復雜可編程邏輯器件
文件頁數: 5/12頁
文件大小: 120K
代理商: PLSI1016-80LT
Specifications
ispLSI 1048
5
USEispLS 1048EAFORNEW
COMMERCAL&INDUSTRAL
DESGNS
18
23
12
14
17
20
20
71.4
41.7
83
9
12
6
6
2
6.5
15
20
12
17
18
18
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4.
f
max (Toggle) may be less than 1/(
t
wh +
t
wl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
MIN. MAX.
31.3
71.4
12
0
16
0
13
7
7
2.7
8.7
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg.
Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1
2
3
5
6
7
9
11
12
13
14
15
16
17
18
19
A
A
B
C
DESCRIPTION
1
PARAMETER
#
2
UNITS
TEST
5
COND.
1
tsu2 + tco1
( )
MIN.
24
30.7
16
18.7
22.7
26.7
26.7
-50
MIN. MAX.
80
50
100
7
5
5
2
6.5
-80
Table 2- 0030A-48/80,70,50
MAX.
-70
External Timing Parameters
Over Recommended Operating Conditions
相關PDF資料
PDF描述
PLSI1016-90LT Low Glitch 16-Bit Voltage Output DAC; Package: PDIP; No of Pins: 16; Temperature Range: 0°C to +70°C
PLSI1016E100LJ Low Glitch 16-Bit Voltage Output DAC; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C
PLSI1016E125LJ 16-Bit Rail-to-Rail Micropower DACs in SO-8 Package; Package: PDIP; No of Pins: 8; Temperature Range: -40°C to +85°C
PLSI1016E-80LJ Electrically-Erasable Complex PLD
ISRT44080
相關代理商/技術參數
參數描述
PLSI1016-80LT44 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016-90LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016-90LT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016-90LT44 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016E100LJ 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
主站蜘蛛池模板: 嘉荫县| 合川市| 固原市| 林周县| 眉山市| 申扎县| 金堂县| 耒阳市| 望奎县| 吉木萨尔县| 平安县| 株洲县| 新乡县| 东乡族自治县| 紫阳县| 始兴县| 河津市| 凌云县| 玉树县| 孙吴县| 广昌县| 丁青县| 屯门区| 大化| 常熟市| 安福县| 康乐县| 彭水| 白水县| 西城区| 游戏| 苏尼特右旗| 颍上县| 临安市| 三门县| 灵寿县| 西宁市| 邹城市| 辉南县| 临夏县| 永福县|