欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: PLSI1016-80LT
英文描述: Electrically-Erasable Complex PLD
中文描述: 電可擦除復雜可編程邏輯器件
文件頁數: 6/12頁
文件大?。?/td> 120K
代理商: PLSI1016-80LT
Specifications
ispLSI 1048
6
USEispLS 1048EAFORNEW
COMMERCAL&INDUSTRAL
46
ORP Bypass Delay
DESGNS
Internal Timing Parameters
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.1
0.9
2.0
8.0
4.6
4.0
5.3
3.9
4.6
8.0
3.3
4.0
5.3
6.7
8.0
21.3
8.6
9.3
10.0
12.7
1.3
3.3
3.3
13.3
11.9
9.9
4.7
2.0
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-50
Inputs
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
GRP
t
grp1
t
grp4
t
grp8
t
grp12
t
grp16
t
grp48
GLB
t
4ptbp
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gr
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 48 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6.0
0.5
1.5
6.0
3.5
3.0
4.0
3.0
3.5
6.0
2.5
3.0
4.0
5.0
6.0
16.0
6.5
7.0
7.5
9.5
1.0
2.5
2.5
10.0
9.0
7.5
3.5
1.5
MIN. MAX.
-70
5.3
1.5
0.8
5.0
2.9
2.5
3.3
2.5
2.9
5.0
2.1
2.5
3.3
4.2
5.0
13.3
5.4
6.5
7.6
8.4
0.8
2.1
2.1
8.3
8.8
6.3
3.2
1.3
MIN. MAX.
-80
Table 2- 0036A-48/80,70,50.eps
相關PDF資料
PDF描述
PLSI1016-90LT Low Glitch 16-Bit Voltage Output DAC; Package: PDIP; No of Pins: 16; Temperature Range: 0°C to +70°C
PLSI1016E100LJ Low Glitch 16-Bit Voltage Output DAC; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C
PLSI1016E125LJ 16-Bit Rail-to-Rail Micropower DACs in SO-8 Package; Package: PDIP; No of Pins: 8; Temperature Range: -40°C to +85°C
PLSI1016E-80LJ Electrically-Erasable Complex PLD
ISRT44080
相關代理商/技術參數
參數描述
PLSI1016-80LT44 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016-90LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016-90LT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016-90LT44 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1016E100LJ 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
主站蜘蛛池模板: 沙坪坝区| 乡城县| 佛学| 若尔盖县| 太和县| 水城县| 慈利县| 大竹县| 嘉祥县| 东兴市| 新邵县| 米易县| 珲春市| 射阳县| 江川县| 溆浦县| 观塘区| 南安市| 乐都县| 台前县| 革吉县| 沧源| 文水县| 青铜峡市| 扬州市| 长垣县| 小金县| 乌苏市| 大庆市| 缙云县| 赤壁市| 女性| 灵武市| 迁西县| 承德县| 临夏县| 拉萨市| 福建省| 山西省| 武平县| 焉耆|