- 您現在的位置：買賣IC網 > PDF目錄361005 > PLSI1016-80LT Electrically-Erasable Complex PLD PDF資料下載
參數資料
| 型號： | PLSI1016-80LT |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復雜可編程邏輯器件 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 120K |
| 代理商： | PLSI1016-80LT |
Specifications
ispLSI 1048
8
USEispLS 1048EAFORNEW
= Clock (max) + Reg h - Logic
=
(
t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(
t
gh
) - (
t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#50 + #40 + #52
)
+
(
#39
) - (
#20 + #28 + #35
)
5.0 ns = (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5)
t
co
= Clock (max) + Reg co + Output
=
(
t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(
t
gco
)
+
(
t
orp +
t
ob
)
=
(
#50 + #40 + #52
)
+
(
#40
)
+
(
#45 + #47
)
21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0)
COMMERCAL&INDUSTRAL
DESGNS
ispLSI 1048 Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
#33
20 PT
XOR Delays
Control
PTs
#42, 43,
44
GRP
Delay
#27, 29,
30, 31, 32
Input
RST
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP 4
#28
GLB Reg Bypass
#37
ORP Bypass
#46
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#21 - 25
#34, 35, 36
#51, 52,
53, 54
#50
#45
Reset
Ded. In
#26
#55
#55
#38, 39,
40, 41
#48, 49
#47
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
t
su
= Logic + Reg su - Clock (min)
=
(
t
iobp +
t
grp4 +
t
20ptxor
)
+
(
t
gsu
) - (
t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#20 + #28 + #44
)
5.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (3.0 + 3.0 + 3.5)
t
h
= Clock (max) + Reg h - Logic
=
(
t
iobp +
t
grp4 +
t
ptck(max)
)
+
(
t
gh
) - (
t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#20 + #28 + #44
)
+
(
#39
) - (
#20 + #28 + #35
)
6.0 ns = (3.0 + 3.0 + 7.5) + (6.0) - (3.0 + 3.0 + 7.5)
t
co
= Clock (max) + Reg co + Output
=
(
t
iobp +
t
grp4 +
t
ptck(max)
)
+
(
t
gco
)
+
(
t
orp +
t
ob
)
=
(
#20 + #28 + #44
)
+
(
#40
)
+
(
#45 + #47
)
22.5 ns = (3.0 + 3.0 +7.5) + (2.5) + (3.5 + 3.0)
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
= Logic + Reg su - Clock (min)
=
(
t
iobp +
t
grp4 +
t
20ptxor
)
+
(
t
gsu
) - (
t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#50 + #40 + #52
)
6.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (5.0 + 2.5 + 1.0)
t
h
1. Calculations are based upon timing specifications for the ispLSI 1048-70.
相關PDF資料 |
PDF描述 |
|---|---|
| PLSI1016-90LT | Low Glitch 16-Bit Voltage Output DAC; Package: PDIP; No of Pins: 16; Temperature Range: 0°C to +70°C |
| PLSI1016E100LJ | Low Glitch 16-Bit Voltage Output DAC; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PLSI1016E125LJ | 16-Bit Rail-to-Rail Micropower DACs in SO-8 Package; Package: PDIP; No of Pins: 8; Temperature Range: -40°C to +85°C |
| PLSI1016E-80LJ | Electrically-Erasable Complex PLD |
| ISRT44080 | |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PLSI1016-80LT44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1016-90LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1016-90LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1016-90LT44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1016E100LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
發布緊急采購，3分鐘左右您將得到回復。