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| 型號(hào)： | PSD303V-A-90JM |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Single Output LDO, 3.0A, Fixed(1.5V), Fast Transient Response, Low Quiescent Current 5-DDPAK/TO-263 0 to 70 |
| 中文描述： | 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備 |
| 文件頁數(shù)： | 17/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD303V-A-90JM |
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PSD3XX Famly
14
Function
PADA and PADB Inputs
A19/CSI
When the PSD is configured to use CSI and while CSI is a logic 1, the PAD
deselects all of its outputs and enters a power-down mode (see Tables 12
and 13). When the PSD is configured to use A19, this signal is another
input to the PAD.
These are general purpose inputs from Port C. See Figure 4, Note 3.
These are address inputs.
These are inputs from the page register (not available on 3X1 versions).
This is the read pulse or strobe input. (DS not available on 3X1 versions).
This is the write pulse or R/W select signal.
This is the ALE or AS input to the chip. Use to demultiplex address
and data.
This deselects all outputs from the PAD; it can not be used in product
term equations. See Tables 10 and 11.
A16–A18
A11–A15
P0–P3
RD/E/DS
WR or R/W
ALE/AS
RESET
PADA Outputs
These are internal chip-selects to the 8 EPROM banks. Each bank can
be located on any boundary that is a function of one product term of the
PAD address inputs.
This is an internal chip-select to the SRAM. Its base address location is
a function of one term of the PAD address inputs.
This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Tables 5A and 5B.
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode controls the input direction of Port A.
CSADIN is gated externally to the PAD by the internal read signal. When
CSADIN and a read operation are active,
data presented on Port A
flows out of AD0/A0–AD7/A7
. This chip-select can be placed on any
boundary that is a function of one product term of the PAD inputs.
See Figure 5B.
This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode, controls the output direction of Port A.
CSADOUT1 is gated externally to the PAD by the ALE signal. When
CSADOUT1 and the ALE signal are active, the
address presented on
AD0/A0–AD7/A7 flows out of Port A
. This chip-select can be placed on
any boundary that is a function of one product term of the PAD inputs.
See Figure 5B.
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode, controls the output direction of Port A.
CSADOUT2 must include the write-cycle control signals as part of its
product term. When CSADOUT2 is active, the
data presented on
AD0/A0–AD7/A7 flows out of Port A
. This chip-select can be placed on
any boundary that is a function of one product term of the PAD inputs.
See Figure 5B.
ES0–ES7
RS0
CSIOPORT
CSADIN
CSADOUT1
CSADOUT2
PADB Outputs
CS0–CS3
These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD inputs.
These chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.
These chip-select outputs can be routed through Port C. See Figure 4,
Note 3. Each of them is a function of one product term of the PAD inputs.
CS4–CS7
CS8–CS10
Table 4.
PSD3XX
PADA and
PADB
Functions
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