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參數資料
| 型號： | PSD303V-A-90JM |
| 廠商： | 意法半導體 |
| 英文描述： | Single Output LDO, 3.0A, Fixed(1.5V), Fast Transient Response, Low Quiescent Current 5-DDPAK/TO-263 0 to 70 |
| 中文描述： | 低成本現場可編程微控制器外圍設備 |
| 文件頁數： | 26/85頁 |
| 文件大?。?/td> | 691K |
| 代理商： | PSD303V-A-90JM |
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PSD3XX Famly
23
12.0
Control Signals
(cont.)
12.5 A19/CSI
This pin is configured using PSDsoft to be either a chip select for the entire PSD device or
an additional PAD input. If your MCU can generate a chip-select signal, and you wish to
save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic
input.
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When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD
in normal operation. However, when a high is detected on the pin, the PSD
enters Power-down Mode. See Tables 7A and 7B for information on signal states
during Power-down Mode. See section 16 for details about the reduction of power
consumption.
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When configured as A19, the pin can be used as an additional input to the PADs.
It can be used for address or logic. It can also be ALE/AS dependent or a transparent
input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always
enabled.
Port
Configuration Mode(s)
State
AD0–A0/AD15/A15
All
MCU I/O
Tracking AD0/A0-AD7/A7
Latched Address Out
MCU I/O
Chip Select Outputs, CS0–CS7, CMOS
Chip Select Outputs, CS0–CS7, Open Drain
Address or Logic Inputs, A16-A18
Chip Select Outputs, CS8–CS10, CMOS only
Input (Hi-Z)
Unchanged
Input (Hi-Z)
Logic 1
Unchanged
Logic 1
Hi-Z
Input (Hi-Z)
Logic 1
Port Pins PA0–PA7
Port Pins PB0–PB7
Port Pins PC0–PC2
Table 7A. Signal States During Power-Down Mode
Internal Signal State
During Power-Down
Component
Internal Signal
PAD A and PAD B
CS0–CS10
Logic 1 (inactive)
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
ES0-ES7, RS0
Logic 0 (inactive)
All registers in CSIOPORT
address space, including:
Direction
Data
Page
PMR (turbo bit, ZPSD only)
N/A
All unchanged
Table 7B. Internal States During Power-down
NOTE:
N/A = Not Applicable
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