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參數資料
| 型號： | PSD303V-A-90JM |
| 廠商： | 意法半導體 |
| 英文描述： | Single Output LDO, 3.0A, Fixed(1.5V), Fast Transient Response, Low Quiescent Current 5-DDPAK/TO-263 0 to 70 |
| 中文描述： | 低成本現場可編程微控制器外圍設備 |
| 文件頁數： | 21/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD303V-A-90JM |
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PSD3XX Famly
18
10.
I/OPort
Functions
(
cont.)
10.3 Port B (PB0-PB7)
The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B.
10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode
Each pin of Port B can be individually configured. The following table summarizes what the
control registers (in CSIOPORT space) for Port B do:
NOTE:
1. Default value is the value after reset.
Default
Value
(Note 1)
Register Name
0 Value
1 Value
Port B Pin Register
Sampled logic level
at pin = ‘0’
Pin is configured
as input
Data in DFF = ‘0’
Sampled logic level
at pin = ‘1’
Pin is configured
as output
Data in DFF = ‘1’
X
Port B Direction Register
0
Port B Data Register
0
MCUI/OMode
The default configuration of Port B is MCU I/O. In this mode, every pin can be set
(at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR
FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s
data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the
pin. The contents of the Pin Register indicate the true state of the PSD driving the pin
through the DFF or an external source driving the pin. Pins can be configured as CMOS
or open-drain using
ST
’s PSDsoft software. Open-drain pins require external pull-up
resistors.
Chip Select Output
Alternatively, each bit of Port B can be configured to provide a chip-select output signal
from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is
not limited to chip selects only; they can be used for generic combinatorial logic as well.
Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7
signals is comprised of two product terms.
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