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參數資料
型號: Q67100-H3260
廠商: SIEMENS AG
英文描述: NONVOLATILE MEMORY 8-KBIT EPROM WITH IC BUS INTERFACE
中文描述: 非易失性內存8千比特存儲器總線接口帶IC
文件頁數: 19/53頁
文件大?。?/td> 418K
代理商: Q67100-H3260
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
19
12.99
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below. Specified
t
AC
and
t
OH
parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V /
ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns has to be added to this parameter.
4. If
t
T
is longer than 1 ns, a time (
t
T
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
相關PDF資料
PDF描述
Q67100-H5101 NONVOLATILE MEMORY 8-KBIT EPROM WITH IC BUS INTERFACE
Q67100-Q1019 1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module)
Q67100-Q1030 1M x 4-BIT DYNAMIC RAM LOW POWER 1M x 4-BIT DYNAMIC RAM
Q67100-Q1044 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM
Q67100-Q1049 4M x 4-Bit Dynamic RAM
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