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參數(shù)資料
| 型號： | RM7000-250T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 250 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數(shù)： | 20/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
20
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
4.13 Joint TLB
For fast virtual-to-physical address translation, the RM7000 uses a large, fully associative TLB
that maps virtual pages to their corresponding physical addresses. As indicated by its name, the
joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as pairs
of even/odd entries, and maps a virtual address and address space identifier into the large, 64 GB
physical address space. By default, the JTLB is configured as 48 pairs of even/odd entries. The 64
even/odd entry optional configuration is set at boot time.
Two mechanisms are provided to assist in controlling the amount of mapped space, and the
replacement characteristics of various memory regions. First, the page size can be configured, on a
per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in 4X multiples). A CP0 register,
PageMask, is loaded with the desired page size of a mapping, and that size is stored into the TLB
along with the virtual address when a new entry is written. Thus, operating systems can create
special purpose maps; for example, a typical frame buffer can be memory mapped using only one
TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM7000 provides a random replacement algorithm to select a TLB entry to be written with a new
mapping; however, the processor also provides a mechanism whereby a system specific number of
mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism
allows the operating system to guarantee that certain pages are always mapped for performance
reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time
systems by allowing deterministic access to critical software.
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine whether the coherency algorithm is:
uncached, write-back, write-through with write-allocate, write-through without write-allocate,
write-back with secondary and tertiary bypass. Note that both of the write-through protocols
bypass both the secondary and the tertiary caches since neither of these caches support writes of
less than a complete cache line.
These protocols are used for both code and data on the RM7000 with data using write-back or
write-through depending on the application. The write-through modes support the same efficient
frame buffer handling as the RM5200 Family, R4700, and R5000.
4.14 Instruction TLB
The RM7000 uses a 4-entry instruction TLB (ITLB) to minimize contention for the JTLB, to
eliminate the critical path of translating through a large associative array, and to save power. Each
ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction address
translation to occur in parallel with data address translation. When a miss occurs on an instruction
address translation by the ITLB, the least-recently used ITLB entry is filled from the JTLB. The
operation of the ITLB is completely transparent to the user.
4.15 Data TLB
The RM7000 uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB.
Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data address
translation to occur in parallel with instruction address translation. When a miss occurs on a data
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