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參數資料
| 型號： | RM7000-250T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 250 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數： | 30/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-250T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
30
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 9 Processor Block Read
The read latency is four cycles (
ValidOut*
to
ValidIn*
), and the response data pattern is
DDxxDD. Figure 10 shows a processor block write where the processor was programmed with
write-back data rate boot code 2, or DDxxDDxx.
Finally, Figure 11 shows a typical sequence resulting in two outstanding reads both with initial
tertiary cache accesses, as explained in the following sequence.
1. The processor issues a read which misses in the tertiary cache.
2. The external agent takes control of the bus in preparation for returning data to the processor.
3. The processor encounters another internal cache miss and therefore asserts
PRqst*
in order to
regain control of the bus.
4. The external agent pulses
PAck*
, returning control of the bus to the processor.
5. The processor issues a read for the second miss.
6. The second cycle also misses in the tertiary.
7. The
RspSwap*
pin is asserted to denote the out of order response. Not shown in the figure is
the completion of the data transfer for the second miss, or any of the data transfer for the first
miss.
8. The external agent retakes control of the bus and begins returning data (out of order) for the
second miss to the processor.
SysClock
SysAD
Addr
Data0
Data1
Data2
Data3
SysCmd
Read
NData
NData
NData
NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
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相關代理商/技術參數 |
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|---|---|
| RM7000263S | 制造商:QED 功能描述:* |
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| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
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