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參數(shù)資料
| 型號： | S29CL016J0MFAM100 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 40/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL016J0MFAM100 |
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September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
43
Pr el im i n a r y
3. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-
out without programming or erasing the PPB.
9.2.1
Programming PPB
The PPB Program Command is used to program, or set, a given PPB. The first three cycles in the
PPB Program Command are standard unlock cycles. The fourth cycle in the PPB Program Com-
mand executes the pulse which programs the specified PPB. The user must wait either 100 s or
until DQ6 stops toggling before executing the fifth cycle, which is the read verify portion of the
PPB Program Command. The sixth cycle outputs the status of the PPB Program operation.
In the event that the program PPB operation was not successful, the user can loop directly to the
fourth cycle of the PPB Program Command to perform the program pulse and read verification
again. After four unsuccessful loops through the program pulse and read verification cycles the
PPB programming operation should be considered a failure.
Figure 9.2 PBB Program Operation
9.2.2
Erasing PPB
The All PPB Erase command is used to erase all the PPBs in bulk. There are no means for indi-
vidually erasing a specific PPB. The first three cycles of the PPB Erase command are standard
unlock cycles. The fourth cycle executes the erase pulse to all the PBBs. The user must wait ei-
ther 20ms or until DQ6 stops toggling before executing the fifth cycle, which is the read verify
portion of the PPB Erase Command. The sixth cycle outputs the status of the PPB Erase
operation.
In the event that the erase PPB operation was not successful, the user can loop directly to the
fourth cycle of the All PPB Erase Command to perform the erase pulse and read verification
again. After four unsuccessful loops through the erase pulse and read verification cycles, the PPB
erasing operation should be considered a failure.
Note:
Either poll DQ6 in the
small bank and wait for
it to stop toggling OR
wait 100us
DQ0=1?
Write 0x68 to SG+WP
Write 0x48 to SG+WP
Read from SG+WP
YES
NO
5
th attempt?
YES
NO
Note: Reads from the
small bank at this point
return the status of the
operation, not read array
data.
Done
Error
Write 0xAA to 0x555
Write 0x55 to 0x2AA
Write 0x60 to 0x555
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