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參數資料
| 型號： | SC427MLTRT |
| 廠商： | Semtech |
| 文件頁數： | 22/33頁 |
| 文件大小： | 894K |
| 描述： | IC REG DL BUCK/LINEAR 32MLPQ |
| 標準包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調，10A |
| 電壓/電流 - 輸出 2： | 5V，200mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 無 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC427MLDKR |
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SC417/SC427
22
nal bias voltage at V5V and the ENL pin is used to program
the VIN UVLO feature, the voltage at FBL needs to be higher
than 750mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing V
IN
UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO
threshold and stays above 1V, then the switcher will turn
off but the LDO will remain on.
Additional protection logic is included in the SC417/SC427
to allow for maximum flexibility of the IC and controlled
starting in self-biased mode. In self-biased mode where the
LDO and PWM are started at the same time, the PWM
output will not start until the LDO reaches 90% of its final
value. This prevents overloading the current limited LDO
output during LDO start up. When using the LDO as an
independent output, it is desirable to be able to turn the
LDO on and off independent of the PWM output. This is
accomplished by checking the PWM PGOOD output during
start-up. If PGOOD is high when the LDO turns on then the
two outputs are assumed to be independent and the LDO
start-up will not effect the PWM. If the PGOOD output is
low then the part is assumed to be in self-biased mode and
the PWM turn-on is delayed until the LDO start-up is 90%
complete.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
ENL pin
VLDO output
V
IN
input voltage
When the ENL pin is high and V
IN
is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the LDO output voltage is near zero, the LDO initiates a
current-limited start-up (typically 85mA) to charge the output
capacitor. When V
LDO
has reached 90% of the final value (as
sensed at the FBL pin), the LDO current limit is increased to
~200mA and the LDO output is quickly driven to the nominal
value by the internal LDO regulator (see Figure 10).
1.
2.
3.
V
VLDO
Final
0% of V
VLDO
Final
Constant current startup
Voltage regulating with
~200mA current limit
Figure 10 LDO Start-Up
LDO Switch-Over Operation
The SC417/SC427 includes a switch-over function for the
LDO. The switch-over function is designed to increase
efficiency by using the more efficient DC-DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function con-
nects the VLDO pin directly to the VOUT pin using an
internal switch. When the switch-over is complete the
LDO is turned off, which results in a power savings and
maximizes efficiency. If the LDO output is used to bias the
SC417/SC427, then after switch-over the device is self-
powered from the switching regulator with the LDO
turned off.
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. There are two methods that
determine the switch-over of V
LDO
to V
OUT
.
In the first method, the LDO is already in regulation and
the DC-DC converter is later enabled. As soon as the
PGOOD output goes high, the 32 cycles are started. The
voltages at the VLDO and VOUT pins are then compared;
if the two voltages are within ?00mV of each other, the
VLDO pin connects to the VOUT pin using an internal
switch, and the LDO is turned off.
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90% of its final
value. At this time, the VLDO and VOUT pins are compared,
and if within ?00mV the switch-over occurs and the LDO
is turned off.
Switch-over Limitations on VOUT and VLDO
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are limitations
on permissible combinations of these pins. Consider the
case where V
OUT
is programmed to 3.0V and V
LDO
is pro-
Applications Information (continued)
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