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參數資料
| 型號： | TFP501PZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 24/24頁 |
| 文件大小： | 373K |
| 代理商： | TFP501PZPG4 |
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B JULY 2001 REVISED AUGUST 2002
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1 pixel/clock
PIXS = Low
ST=Low,
CL=10 pF
1.9
ns
OCK_INV = High
ST=High, CL=10 pF
1.9
ns
Setup time, data and control signal to
2 pixel/clock
PIXS = High
ST=Low,
CL=10 pF
2.9
ns
tsu(2)
Setup time, data and control signal to
rising edge of ODCK (see Note 11)
STAG = High
OCK_INV = High
ST=High, CL=10 pF
2.9
ns
2 pixel & STAG
PIXS = High
ST=Low,
CL=10 pF
2.0
ns
STAG = Low
OCK_INV = High
ST=High, CL=10 pF
2.0
ns
1 pixel/clock
PIXS = Low
ST=Low, CL=10 pF
0.5
ns
Hold time, data and control signal to rising
OCK_INV = High
ST=High, CL=10 pF
0.5
ns
th(2)
Hold time, data and control signal to rising
edge of ODCK (see Note 11)
2 pixel & STAG
PIXS = High
ST=Low,
CL=10pF
1.4
ns
STAG = Low
OCK_INV = High
ST=High,
CL=10pF
1.4
ns
f(ODCK)
ODCK frequency
PIXS = Low
25
165
MHz
f(ODCK)
ODCK frequency
PIXS = High
12.5
82.5
MHz
ODCK duty-cycle
40%
50%
60%
td(PDL)
Delay from PD low to Hi-Z outputs
18
ns
td(PDOL) Delay from PDO low to Hi-Z outputs
18
ns
t(HSC)
Time between DE transitions to SCDT low
(see Note 13)
165 MHz
25
ms
tt(FSC)
Time from DE low to SCDT high (see Note
13)
8
trans(DE)
td(st)
ODCK latching edge to QE[23:0] data
output
STAG = Low, PIXS = High
0.5
t(pixel)
ns
trans(DE) is one transition (low-to-high or high-to-low) of the DE signal.
NOTES: 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
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