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參數資料
| 型號： | TFP501PZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 7/24頁 |
| 文件大小： | 373K |
| 代理商： | TFP501PZPG4 |
TFP501
PanelBus HDCP DIGITAL RECEIVER
SLDS127B JULY 2001 REVISED AUGUST 2002
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TFP501 modes of operation
The TFP501 provides system design flexibility and value by providing the system designer with configurable
options or modes of operation to support varying system architectures. The following table outlines the various
panel modes that can be supported along with appropriate external control pin settings.
PANEL
PIXEL RATE
ODCK LATCH EDGE
ODCK
DFO
PIXS
OCK_INV
TFT or 16-bit DSTN
1 pixel/clock
Falling
Free run
0
TFT or 16-bit DSTN
1 pixel/clock
Rising
Free run
0
1
TFT
2 pixel/clock
Falling
Free run
0
1
0
TFT
2 pixel/clock
Rising
Free run
0
1
24-bit DSTN
1 pixel/clock
Falling
Gated Low
1
0
None
1 pixel/clock
Rising
Gated Low
1
0
1
24-bit DSTN
2 pixel/clock
Falling
Gated Low
1
0
24-bit DSTN
2 pixel/clock
Rising
Gated Low
1
TFP501 output driver configurations
The TFP501 provides flexibility by offering various output driver features that can be used to optimize power
consumption, ground-bounce and power-supply noise. The following sections outline the output driver features
and their effects.
Output driver power down (PDO = low.) Pulling PDO low places all the output drivers, except CTL1 and SCDT,
into a high-impedance state. A weak pulldown (approximately 10
A) gradually pulls these high-impedance
outputs to a low level to prevent the outputs from floating. The SCDT output, which indicates link-disabled or
link-inactive, can be tied directly to the PDO input to disable the output drivers when the link is inactive or when
the cable is disconnected. An internal pullup on the PDO pin defaults the TFP501 to the normal nonpower-down
output drive mode if left unconnected.
Drive strength (ST = high for high drive strength, ST = low for low drive strength.) The TFP501 allows for
selectable output drive strength on the data, control, and ODCK outputs. See the dc specifications table for the
values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two times
the drive as the low output drive strength.
Time staggered pixel output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high.)
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 T(ODCK). (T(ODCK) is the period of ODCK. The ODCK
period is 2 t(pixel) when in 2-pixel/clock mode.)
Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP501
drive strength and staggered pixel options allow flexibility to reduce system power supply noise, ground bounce
and EMI.
Power management. The TFP501 offers several system power management features. The output driver
power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers
except SCDT and CTL1 are driven to a high-impedance state while the rest of the device circuitry remains active.
The TFP501 power down (PD = low) is a complete power down in that it powers down the digital core, the analog
circuitry and output drivers. All output drivers are placed into a high-impedance state. All inputs are disabled
except for the PD input. The TFP501 does not respond to any digital or analog inputs until PD is pulled high.
Both PDO and PD have internal pullups so if left unconnected they default the TFP501 to normal operating
modes.
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