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參數資料
| 型號： | TFP510PAPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-64 |
| 文件頁數： | 11/27頁 |
| 文件大?。?/td> | 383K |
| 代理商： | TFP510PAPG4 |
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TFP510
TI PanelBus DIGITAL TRANSMITTER
SLDS146B JANUARY 2002 REVISED DECEMBER 2002
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register descriptions (continued)
CTL_2_MODE
Sub-Address = 09
Read/Write
Default = 0x00
7
6
5
4
3
2
1
0
VLOW
MSEL[3:1]
TSEL
RSEN
HTPLG
MDI
MDI: This read/write register contains the monitor detect interrupt mode.
0: Detected logic level change in detection signal (to clear, write 1 to this bit)
1: Logic level remains the same
HTPLG: This read-only register contains the hot plug detection input logic state.
0: Low level detected on the EDGE/HTPLG pin (pin 9)
1: High level detected on the EDGE/HTPLG pin (pin 9)
RSEN: This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems.
0: A powered-on receiver is not detected
1: A powered-on receiver is detected (i.e., connected to the DVI transmitter outputs)
TSEL: This read/write register contains the interrupt generation source select.
0: Interrupt bit (MDI) is generated by monitoring RSEN
1: Interrupt bit (MDI) is generated by monitoring HTPLG
MSEL[3:1]: This read/write register contains the source select of the monitor sense output pin.
000: Disabled. MSEN output high
001: Outputs the MDI bit (interrupt)
010: Outputs the RSEN bit (receiver detect)
011: Outputs the HTPLG bit (hot plug detect)
VLOW: This read-only register indicates the VREF input level.
0: This bit is a logic level 0 if the VREF analog input selects high-swing inputs.
1: This bit is a logic level 1 if the VREF analog input selects low-swing inputs.
CTL_3_MODE
Sub-Address = 0A
Read/Write
Default = 0x80
7
6
5
4
3
2
1
0
DK[3:1]
DKEN
RSVD
CTL[2:1]
RSVD
CTL[2:1]:This read/write register contains the values of the two CTL[2:1] bits that are output on the DVI port during
the blanking interval. CTL[3] is not available on the TFP510 because it is inetrnally generated by the HDCP
circuitry.
DKEN: This read/write register controls the data de-skew enable.
0: Data de-skew is disabled; the values in DK[3:1] are not used.
1: Data de-skew is enabled; the de-skew setting is controlled through DK[3:1].
DK[3:1]: This read/write register contains the de-skew setting, each increment adjusts the skew by t(STEP).
000: Step 1 (minimum setup/maximum hold)
001: Step 2
010: Step 3
011: Step 4
100: Step 5 (default)
101: Step 6
110: Step 7
111: Step 8 (maximum setup/minimum hold)
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