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參數(shù)資料
| 型號： | TFP510PAPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-64 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大小： | 383K |
| 代理商： | TFP510PAPG4 |
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TFP510
TI PanelBus DIGITAL TRANSMITTER
SLDS146B JANUARY 2002 REVISED DECEMBER 2002
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I2C interface (continued)
Following a start condition, each I2C device decodes the slave address. The TFP510 responds with an
acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.
During subsequent sub-address and data cycles, the TFP510 responds with acknowledge as shown in
Figure 11. The sub-address is auto-incremented after each data cycle.
The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device
may drive the SDA signal low. The master indicates a not acknowledge condition (/A) by keeping the SDA signal
high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 12.
In order to minimize the number of bits that must be transferred for the HDCP link integrity check, a second read
format is supported. This access, shown in Figure 13, has an implicit sub-address equal to the starting location
for the HDCP receiver link verification response (R i).
The slave address consists of 7 bits of address along with 1 bit of read/write information (i.e., read = 1 and
write = 0) as shown in Figures 12 and 13. For the TFP510 the slave addresses are 0x70 for write cycles and
0x71 for read cycles.
S
Slave Address
W
A
Sub-Address
A
Data
A
Data
A
P
From Master
A Acknowledge
From Slave
S Start condition
P Stop Conditon
R Read Condition = 1
W Write Condition = 0
Figure 12. I2C Write Cycle
S
Slave Address
W
A
Sub-Address
A
Sr
Slave Address
R
A
Data
A
Data
/A
P
From Master
A Acknowledge
From Slave
S Start condition
/A Not acknowledge (SDA high)
P Stop Conditon
R Read Condition = 1
Sr Restart Condition
W Write Condition = 0
Figure 13. I2C Read Cycle
S
Slave Address
R
A
Data
A
Data
/A
P
From Master
A Acknowledge
From Slave
S Start condition
/A Not acknowledge (SDA high)
P Stop Conditon
R Read Condition = 1
Figure 14. HDCP Port Link Integrity Message Read
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