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參數(shù)資料
| 型號： | TFP510PAPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-64 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大小： | 383K |
| 代理商： | TFP510PAPG4 |
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TFP510
TI PanelBus DIGITAL TRANSMITTER
SLDS146B JANUARY 2002 REVISED DECEMBER 2002
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I2C interface
The I2C interface is used to access the internal registers. This two-pin interface consists of the SCL clock line
and the SDA serial data line. The basic I2C access cycles are shown in Figures 9 and 10.
Start Condition (S)
Stop Condition (P)
SDA
SCL
Figure 10. I2C Start and Stop Conditions
The basic access write cycle consists of the following:
1.
A start condition
2.
A slave address cycle
3.
A sub-address cycle
4.
Any number of data cycles
5.
A stop condition
The basic access read cycle consists of the following:
1.
A start condition
2.
A slave write address cycle
3.
A sub-address cycle
4.
A restart condition
5.
A slave read address cycle
6.
Any number of data cycles
7.
A stop condition
The start and stop conditions are shown in Figure 9. The high-to-low transition of SDA while SCL is high defines
the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,
data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving
device. Thus, each data/address cycle contains 9 bits as shown in Figure 10.
SCL
1
2
3
4
5
6
7
8
9
SDA
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
1
Slave Address
Sub-Address
Data
Stop
89
Figure 11. I2C Access Cycles
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