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| 型號： | THS10064CDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大小： | 527K |
| 代理商： | THS10064CDAR |
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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
24
ADC CONTROL REGISTERS
Control Register 0, Write Only (see Table 8)
RA1
RA0
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
MODE
VREF
Table 9. Control Register 0 Bit Functions
BITS
RESET
VALUE
NAME
FUNCTION
0
VREF
Vref select:
Bit 0 = 0
→ The internal reference is selected
Bit 0 = 1
→ The external reference voltage is selected
1
0
MODE
Continuous conversion mode/single conversion mode
Bit 1 = 0
→ Continuous conversion mode is selected
An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the
CONV_CLK signal a new converted value is written into the FIFO.
Bit 1 = 1
→ Single conversion mode is selected
In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the
THS10064 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the
selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected
channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is
satisfied.
2
0
PD
Power down.
Bit 2 = 0
→ The ADC is active
Bit 2 = 1
→ Power down
The reading and writing to and from the digital outputs is possible during power down. It is also possible to
read out the FIFO.
3, 4
0,0
CHSEL0,
CHSEL1
Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.
5,6
1,0
DIFF0, DIFF1
Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10.
7
0
SCAN
Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10.
8,9
0,0
TEST0,
TEST1
Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC operation.
Refer to Table 11 for selection of the three different test voltages. The control signal DATA_AV is disabled in
the test mode. Test voltage readings have to be done independent from DATA_AV. To get the THS10064
back to the normal operating mode, apply the initialization routine.
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| THS10064CDARG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064DA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS10064EVM | 制造商:Texas Instruments 功能描述:THS10064 10-BIT, 6 MSPS, DC EVM - Bulk |
| THS10064IDA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064IDAG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10B 6 MSPS ADC Quad Ch. DSP/uP Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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