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參數資料
| 型號： | THS10064CDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數： | 38/42頁 |
| 文件大小： | 527K |
| 代理商： | THS10064CDAR |
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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
5
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
Clock cycle of the internal clock oscillator
151
167
175
ns
1 analog input
1.5
×tc
t1
Pulse duration CONVST
2 analog inputs
2.5
×tc
ns
t1
Pulse duration, CONVST
3 analog inputs
3.5
×tc
ns
4 analog inputs
4.5
×tc
td(A)
Aperture time
1
ns
1 analog input
2
×tc
td2
Delay time between consecutive start of single
2 analog inputs
3
×tc
ns
td2
yg
conversion
3 analog inputs
4
×tc
ns
4 analog inputs
5
×tc
1 analog input,
TL = 1
6.5
×tc + 15
Delay time, DATA_AV becomes active for the
2 analog inputs, TL = 2
7.5
×tc +15
ns
y,
_
trigger level condition: TRIG0 = 0, TRIG1 = 0
3 analog inputs, TL = 3
8.5
×tc +15
ns
4 analog inputs, TL = 4
9.5
×tc +15
1 analog input,
TL = 4
3
×t2 +6.5×tc+15
td(DATA AV)
Delay time, DATA_AV becomes active for the
2 analog inputs, TL = 4
t2 +7.5×tc+15
ns
td(DATA_AV)
y,
_
trigger level condition: TRIG0 = 1, TRIG1 = 0
3 analog inputs, TL = 6
t2 +8.5×tc+15
ns
4 analog inputs, TL = 8
t2 +9.5×tc+15
1 analog input,
TL = 8
7
×t2 +6.5×tc+15
Delay time, DATA_AV becomes active for the
2 analog inputs, TL = 8
3
×t2 +7.5×tc+15
ns
y,
_
trigger level condition: TRIG0 = 0, TRIG1 = 1
3 analog inputs, TL = 9
2
×t2 +8.5×tc+15
ns
4 analog inputs, TL = 12
2
×t2 +9.5×tc+15
D l
ti
DATA AV b
ti
f
th
1 analog input,
TL = 14
13
×t2 +6.5×tc+15
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1 TRIG1 = 1
2 analog inputs, TL = 12
5
×t2 +7.5×tc+15
ns
(
_
)
trigger level condition: TRIG0 = 1, TRIG1 = 1
3 analog inputs, TL = 12
3
×t2 +8.5×tc+15
(1) Timing parameters are ensured by design but are not tested.
(2) See Figure 26.
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
RA0
RA1
CONV_CLK (CONVST)
DATA_AV
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
DA (TSSOP) PACKAGE
(TOP VIEW)
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相關代理商/技術參數 |
參數描述 |
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| THS10064CDARG4 | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064DA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS10064EVM | 制造商:Texas Instruments 功能描述:THS10064 10-BIT, 6 MSPS, DC EVM - Bulk |
| THS10064IDA | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064IDAG4 | 功能描述:模數轉換器 - ADC 10B 6 MSPS ADC Quad Ch. DSP/uP Interface RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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