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參數資料
| 型號： | THS10064CDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數： | 8/42頁 |
| 文件大小： | 527K |
| 代理商： | THS10064CDAR |
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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
16
Table 2 shows the maximum conversion rate in the single conversion mode.
Table 2. Maximum Conversion Rate in Single Conversion Mode(1)
CHANNEL CONFIGURATION
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
3 MSPS
2 single-ended channels
2
2 MSPS
3 single-ended channels
3
1.5 MSPS
4 single-ended channels
4
1.2 MSPS
1 differential channel
1
3 MSPS
2 differential channels
2
2 MSPS
1 single-ended and 1 differential channel
2
2 MSPS
2 single-ended and 1 differential channels
3
1.5 MSPS
(1) Maximum conversion rate with respect to the typical internal clock speed (i.e. 6 MPS * (tc/t2).
SINGLE CONVERSION MODE
In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold
stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the
selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be
selected according to Table 13.
Figure 26 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be
selected to be sampled simultaneously (see Table 2).
CONVST
AIN
Sample N
t1
td(A)
td2
td(DATA_AV)
DATA_AV,
Trigger Level = 1
Figure 26. Timing of Single Conversion Mode
The time (td2) between consecutive starts of single conversions is dependent on the number of selected analog input
channels. The time td(DATA_AV), untilDATA_AV becomes active is given by: td(DATA_AV) = tpipe + n × tc. This equation
is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger
level conditions refer to the timing specifications of single conversion mode.
CONTINUOUS CONVERSION MODE
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In
continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock
signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.
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| THS10064CDARG4 | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064DA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS10064EVM | 制造商:Texas Instruments 功能描述:THS10064 10-BIT, 6 MSPS, DC EVM - Bulk |
| THS10064IDA | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064IDAG4 | 功能描述:模數轉換器 - ADC 10B 6 MSPS ADC Quad Ch. DSP/uP Interface RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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