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參數資料
| 型號： | THS8083-95CPZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100 |
| 文件頁數： | 9/61頁 |
| 文件大小： | 239K |
| 代理商： | THS8083-95CPZP |
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2–3
Ext. Logic
PFD_FREEZE
CS
THS8083
HS
Frame Period
PFD_FREEZE High in VBI on Lines Where CS
Has Multiple Rising/Falling Edges Per Line
Option 1: Using PFD_FREEZE
Sync.
Separator
CS
THS8083
HS
Option 2: Using HS Derived From CS
PFD_FREEZE
VS
Figure 2–4. Using THS8083 With a Composite Sync
Note that the slicer will only work when no video levels are lower than the blanking level and when the internal clamp
circuit is used. This is normally satisfied for G and Y channels, but not for U and V channels. To prevent unnecessary
toggling of the CS output signal, the CS output is switched off automatically when mid-level clamping is chosen for
channel 1 (i.e., CLP1_RG=1 in register <CLP_CTRL>). CS can be permanently disabled by setting CS_DIS=1 in
register <AUX_CTRL>. So the state of CS is determined as follows:
CS_ENABLED = NOT (CS_DIS) AND NOT (CLP1_RG).
When CS_ENABLED=0, the CS output will be Hi-Z.
NOTE:
While PFD_FREEZE keeps the DTO output frequency constant, it does not disable the
phase/frequency detector (PFD) from internally updating its error value at every active edge
on HS. Therefore, when deasserting PFD_FREEZE and no external sync separator is used,
a discontinuity on the frequency increment to the DTO occurs which will cause an
instantaneous frequency shift. To prevent this, the user should gate the CS signal externally
with the PFD_FREEZE signal as shown in Figure 2.4. This will keep the PFD from updating
during PFD_FREEZE high, since HS will remain low during the VBI. By using both
PFD_FREEZE and gating during the vertical blanking interval, THS8083 can be locked to
signals with a composite sync.
To support sync-on-Y/sync-on-G extraction, the user should provide an external dc biasing to
the Y/G channel. This can be done by establishing a dc clamp through a diode with its cathode
connected to the ac-coupling capacitor (at the side of THS8083) on the AGY channel and
anode connected to a dc level. Since the slicing level is around 1.35 V and the sync amplitude
is ~300 mV, the negative sync-tip should be clamped by the diode to a level of approximately
1.2 V. For example, using a Schottky switching diode (type 1N5711) with a low forward voltage
drop of maximum 0.4 V, the dc level at the anode can be approximately 1.6 V. This level can
be derived through a resistive voltage divider off the power supply.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS8083A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 8 BIT 80 MSPS 3.3V VIDEO AND GRAPHICS |
| THS8083A95 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS |
| THS8083A95PZP | 功能描述:視頻模擬/數字化轉換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| THS8083APZP | 功能描述:視頻模擬/數字化轉換器集成電路 Triple 8B 80 MSPS 3.3V YUV/RGB RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| THS8083APZP | 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083 |
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