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參數資料
| 型號： | THS8083CPZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100 |
| 文件頁數： | 6/61頁 |
| 文件大小： | 266K |
| 代理商： | THS8083CPZP |
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1–8
1.7
THS8083 Terminal Functions Order (Continued)
TERMINAL
I/O/B
TYPE
DESCRIPTION
NAME
NO.
I/O/B
TYPE
DESCRIPTION
DIGITAL CONTROL I/O
SCL
3
B
D
Clock for I2C. Although the device is an I2C slave, this signal can be held low by the device to
signal contention, therefore it is flagged bidirectional.
SDA
4
B
D
Serial data for I2C
I2CA
5
I
D
Address select for I2C
0 = LSB of device address 0
1 = LSB of device address 1
EXT_CLP
99
I
D
External clamp timing pulse. Positive polarity required.
HS
1
I
D
Reference clock input for PLL (horizontal sync input). Polarity selectable via I2C register
<HS_POL>. 5 V tolerant input
VS
2
I
D
Vertical sync input. Polarity selectable via I2C register <VS_POL>. 5 V tolerant input
DHS
55
O
D
Display horizontal sync. This output can be generated as either a delayed version of input
HS or as output pulse from the PLL feedback divider. See Display Horizontal Sync section
in Functional Description.
CS/TEST1
78
O
A/D
Composite sync output. This output will produce a 3-V logic-compatible sliced output of
CH1. When present and enabled, CS will carry the composite sync embedded in Ch1. See
Composite Sync Slicer section in Functional Description. For TI internal testing, this pin
can also be configured as a test pin. Leave unconnected when CS output signal is not
used.
LOCK
100
O
D
Lock detect output
0 = unlocked
1 = locked
PFD_FREEZE
98
I
D
Freezes the PLL output frequency by stopping the PFD output (i.e., keeping last increment
to DTO). See section 2.3 Composite Sync Slicer.
0 = updating
1 = frozen
OE
71
I
D
Output enable for data output busses A and B. Data outputs are active only when OE = L
and the corresponding bus is active for the current output formatter mode (register
OFM_CTRL). When data outputs are not active or when DVDD = 0 V, data output is Hi-Z.
The clock outputs are not affected by OE.
0 = enabled
1 = disabled
RESET
76
I
D
General chip reset (active low). The reset is a synchronous reset. Therefore, a master clock on
XTL1–MCLK needs to be present for proper reset.
TEST I/O
CS/TEST1
78
O
A/D
See description for this terminal under DIGITAL CONTROL I/O higher.
TEST2
79
O
A/D
Test mode analog output 2. Leave unconnected for normal use.
SCAN_TEST
77
I
D
Input for scan-path activation:
0 = disabled
1 = enabled.
This pin MUST be tied low for normal operation and is of use for TI internal testing only.
UNUSED PINS
NC
80, 86,
87, 93,
94
I
A
Not connected. Tie to a fixed high or low level on board.
I = input to device: O = output from device B = bidirectional
A = analog pin: D = digital pin
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