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參數(shù)資料
| 型號： | THS8200PFPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 53/101頁 |
| 文件大小： | 806K |
| 代理商： | THS8200PFPG4 |
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4–40
4.8.6
Summary of Supported Video Formats
RGB WITHOUT
SYNC
RGB SYNC ON G
RGB SYNC ON ALL
YPbPr SYNC ON Y
YPbPr SYNC ON
ALL
Range of input
codes
0 to 1023
64 to 940
64 to 940 on Y;
64 to 960 on Cr and Cb
64 to 940 on Y;
64 to 960 on Cr and Cb
Peak level
700 mV or 1305 mV
1050 mV
Blank level
0.0 V
350 mV
DC level shift during
active video period
0
350 mV
4.9
Test Functions
The user can activate a 75% SMPTE color bar test pattern when the device is configured in VESA mode using the
vesa_colorbars register setting. The width of each color bar can be programmed using the dtg1_vesa_cbar_size
register.
The digital logic in front of the DACs can be completely bypassed and the DACs can be driven directly with levels
programmed from the I2C interface by activating the dac_i2c_cntl register. In this case the dac<n>_cntl registers set
the DAC input codes. A fast or slow ramp signal can be internally generated and sent to the DACs using tst_fastramp
and tst_slowramp registers. This could be useful for a static DAC linearity test.
Alternatively, the input bus can directly drive the DACs when the tst_digbypass register is activated for tests at full
speed.
The delay of the Y channel can be changed in YCbCr modes with respect to Cb and Cr channels by programming
the tst_ydelay register.
Finally, there is a digital output port with data encoded according to ITU-R.BT656. This is a loop-through of the original
input bus, prior to any THS8200 internal processing, and thus only provides standard data when input to the THS8200
is provided in a 10-bit ITU-R BT.656 format. This output bus could be used to connect to a separate NTSC/PAL video
encoder. The data_clk656_on register activates the clock output on this bus and the data_tristate656 register
disables the output bus. It is recommended to disable this output when not in use.
4.10 Power Down
THS8200 implements two power-down modes: dac_pwdn powers down the DAC channels but keeps all digital logic
active; chip_pwdn powers down the digital logic except the I2C interface. Activating both registers enforces a
complete analog/digital power down except for the I2C interface.
4.11 CGMS Insertion
The THS8200 can embed data within the vertical blanking interval, encoded according to the EIA-805 data insertion
standard. CGMS is an implementation of the EIA-805 standard that defines data insertion in component video
interface (CVI) video signals.
The THS8200 supports CGMS data insertion on line 41 of every frame in the 525P format. The data is inserted on
the Y channel only; Pb and Pr channels remain at the blanking level. CGMS data insertion is enabled by activating
the cgms_en register and programming the cgms_header and cgms_payload registers appropriately. The user needs
to program header and payload data in the correct format, as no additional data encoding is done prior to insertion
into the analog DAC output. The THS8200 only performs a play-out function for the programmed data. The CGMS
encoding block assumes that a full 10-bit video range is used in order to determine the 70% of peak-white amplitude
of a logic 1 bit, as prescribed by EIA-805. The CSM does not affect the amplitude of the CGMS data insertion.
CGMS is inserted on line 41 as prescribed by EIA 770 standards for progressive format display of SDTV. Fourteen
bits can be inserted on this line, consisting of 6 bits header and 8 bits payload. The user can directly program these
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