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參數資料
| 型號： | THS8200PFPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數： | 80/101頁 |
| 文件大小： | 806K |
| 代理商： | THS8200PFPG4 |
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1–1
1 Introduction
1.1
Description
THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes,
or any system requiring the conversion of digital component video signals into the analog domain.
THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3
×10-bit, 2 ×10-bit or
1
×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs
or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream.
Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in
which it requests video data from an external (memory) source.
THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard
video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component
video and PC graphics (VESA) formats. A fully-programmable 3
×3 matrixing operation is included for color space
conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2
× oversampled.
Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the
video frequency characteristic.
The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in
order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video
(1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant
video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities
after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with
programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted
either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional
current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves
100% of the DAC’s 11-bit dynamic range for video data.
THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert
ancillary data into the 525P analog component output according to the CGMS data specification
1.2
Features
Three 11-bit 205-MSPS D/A converters with integrated bi-level/tri-level sync insertion
Support for all ATSC video formats (including 1080P) and PC graphics formats (up to UXGA at 75 Hz)
Input
Flexible 10/15/16/20/24/30-bit digital video input interface with support for YCbCr or RGB data, either 4:4:4
or 4:2:2 sampled
Video synchronization via Hsync, Vsync dedicated inputs or via extraction of embedded SAV/EAV codes
according to ITU-R.BT601 (SDTV) or SMPTE274M/SMPTE296M (HDTV)
Glueless interface toTI DVI 1.0 (with HDCP) receivers. Can receive video-over-DVI formats according to
the EIA-861 specification and convert to YPbPr/RGB component formats with separate syncs or embedded
composite sync
Video Processing
Programmable clip/shift/multiply function for operation with full-range or ITU-R.BT601 video range input
data
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