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參數資料
| 型號： | TLE6266G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | 18 MM, PLASTIC, SOP-28 |
| 文件頁數： | 10/50頁 |
| 文件大小： | 1020K |
| 代理商： | TLE6266G |
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Datasheet TLE 6266 G
Version 2.21
18
July 29th, 2005
SPI CLK Monitoring during Cyclic Wake Mode
The TLE 6266 offers a feature to monitor the SPI clock signal (CLK pin) during the cyclic
wake mode. If there are edges on the CLK signal, the IC performs a reset and the RO
pin is set to LOW for t= tWDR (after tWDR a long open window is started and RO is HIGH
again). This feature is activated if the CSN pin is set to HIGH.
6.8
Oscillator
The TLE 6266 has an internal oscillator with +/-15% accuracy. The typ. frequency of the
oscillator is 125kHz. After an internal 64-times frequency divider, this gives an typ. cycle
time tcyc= 0.512ms. The frequency of the oscillator can be measured within the normal,
the Vbat stand-by and the RxD-only mode. This is a timebase test (see Chapter 6.15),
activated via SPI input bit 3 and 4. During this test, the HS3-switch will be activated
cyclically.
6.9
Window Watchdog and Reset
When the output voltage VCC exceeds the reset threshold voltage VRT the reset output
RO is switched HIGH after a delay time tRD. This is necessary for a defined start of the
microcontroller when the application is switched on. As soon as an under-voltage
condition of the output voltage (VCC < VRT) appears, the reset output RO is switched
LOW again. The LOW signal is guaranteed down to an output voltage VCC ≥ 1V. Please
refer to Figure 17, reset timing diagram.
In the cyclic wake HS OFF mode, the watchdog circuit is automatically disabled.Both,
the undervoltage reset and the watchdog reset set all SPI input bits LOW.
Long Open Window
After the delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is
started by opening a long open window. The long open window allows the
microcontroller to run his set-up and to trigger the watchdog via the SPI afterwards.
Within the long open window period a watchdog trigger is alternating detected as a
“rising” or “falling edge” by sampling a HIGH on the SPI input bit 0. The trigger is
accepted when the CSN input becomes HIGH after the transmission of the SPI word.
After every reset condition (watchdog reset, undervoltage reset) as well as a transition
from every mode into the cyclic wake HS ON mode, the watchdog starts the long open
window and the default value of the SPI input bit 0 is LOW.
Closed/Open Window
A correct watchdog trigger immediately results in starting the window watchdog by
opening the closed window followed by the open window (see Figure 18). From now on
the microcontroller has to service the watchdog trigger by inverting the SPI input bit 0
alternating. The “negative” or “positive” edge has to meet the open window time. A
correct watchdog service immediately results in starting the next closed window. Please
refer to Figure 19, watchdog timing diagram.
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