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參數(shù)資料
| 型號： | TLE6266G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | 18 MM, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 7/50頁 |
| 文件大小： | 1020K |
| 代理商： | TLE6266G |
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Datasheet TLE 6266 G
Version 2.21
15
July 29th, 2005
In order to protect the transceiver output stages from being damaged by shorts on the
bus lines, current limiting circuits are integrated. The CANL and CANH output stage
respectively are protected by an additional temperature sensor, that disables them as
soon as the junction temperature exceeds the maximum value. In the temperature shut-
down condition of the CAN output stages receiving messages from the bus lines is still
possible. A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI
output bit 15. The CANH and CANL pins are also protected against electrical transients
which may occur in the severe conditions of automotive environments
6.4
Low Dropout Voltage Regulator
The TLE6266 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance
is less than ± 2%. In addition the regulator circuit drives the internal loads like the CAN-
transceiver circuit. In the cyclic wake HS OFF operation mode the voltage regulator is
switched on and off by a control mechanism (see Chapter 6.5).
The current limitation of the LDO is set to typ. 180mA, to grant that the external capacitor
can be charged quickly. In normal operating mode the external current should be less
then 45mA. This has to guaranteed by the system architecture.
An external reverse current protection is recommended to prevent the output capacitor
from being discharged by negative transients or low input voltage.
Stability of the output voltage is guaranteed for output capacitors CVCC ≥ 100 nF.
Nevertheless a lot of applications require a much larger output capacitance to buffer the
output voltage in case of low input voltage or negative transients. Furthermore the due
function of e.g. the reset and 3V-supervisor circuit are supported by a larger output
capacitance because of their reaction times. Therefore a output capacitance
CVCC ≥ 22 F is recommended.
6.5
LDO activation during Cyclic Wake HS OFF
During the cyclic wake HS OFF mode, the LDO is switched on and off, depending on the
output voltage level, which is monitored internaly. Figure 6 shows a detailed flowchart
of the Vcc control loop and also a graph of the VCC voltage and the thresholds in this
mode. The voltage regulator is switched on as soon as the voltage at VCC falls below the
load-threshold VCC TH to charge an external capacitor. The voltage at VCC starts to
decrease and when the VCC TH threshold is reached again, the capacitor is charged for
additional 1ms. When the nominal voltage level VCC is reached again, the voltage
regulator is automatically deactivated to minimize the current consumption. The period
of charging/decharging is dependant on the external stabilization capacitor at the VCC
pin. If the load is too high and VCC falls below VCC TH for t>3s, a reset is activated.
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