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參數(shù)資料
型號(hào)： TLE7824G
廠商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： GREEN, PLASTIC,SOP-28
文件頁(yè)數(shù)： 20/53頁(yè)
文件大?。?/td> 900K
代理商： TLE7824G
Data Sheet
27
Rev. 3.01, 2008-04-15
TLE7824G
Monitoring / Wake-Up Inputs MON1 … 5 and Wake-Up Event Signalling
10
Monitoring / Wake-Up Inputs MON1 … 5 and Wake-Up Event
Signalling
In addition to a wake-up from SBC Stop / Sleep Mode via the LIN bus line it is also possible to wake-up the
TLE7824G from low power mode via the monitoring/wake-up inputs. These inputs are sensitive to a transition of
the voltage level, either from high to low or vice versa. Monitoring is available in Active Mode and indicates the
voltage level of the inputs via SPI status bits.
A positive or negative voltage edge at MONx in SBC Sleep or Stop Mode results in signalling a wake-up event (via
SBC [DO] to
μC [P1.4] interconnect). After a wake-up via MONx the first transmission of the SPI diagnosis word
in SBC Standby mode indicates the wake-up source. Further SPI status word transmissions show the logic level
at the monitoring input pins.
Note: Immediately before switching the TLE7824G into a SBC power saving mode the activated MONx are
initialized with the actual logic level detected at the MONx. In case a MONx is deactivated it can neither be
used as wake-up source nor can it be used to detect logic levels.
However, there should be a minimum delay of three times “CSN high time” (see Table “SPI Data Input
Timing1)” on Page 43) between activation of MONx and entering a power saving mode.
The monitoring input module consists of an input circuit with pull-up and pull-down current sources to define a
certain voltage level with open inputs and a filter function to avoid wake-up events caused by unwanted voltage
transients at the module inputs.
At a voltage level at the monitoring pins of
V
MON_th < VMONx < 5.5 V the pull-up current source becomes active,
while at 1 V <
V
MONx < VMON_th the pull-down sink is activated (see Figure 11) guaranteeing stable levels at the
monitoring/wake-up inputs. Below and above these voltage ranges the current is minimized to a leakage current
Figure 11
Monitoring Input Block Diagram
+
-
tWK
MONx
Vs
1
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