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| 型號(hào)： | TLE7824G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | GREEN, PLASTIC,SOP-28 |
| 文件頁(yè)數(shù)： | 40/53頁(yè) |
| 文件大小： | 900K |
| 代理商： | TLE7824G |
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Data Sheet
45
Rev. 3.01, 2008-04-15
TLE7824G
Timing Diagrams
17
Timing Diagrams
Figure 13
SPI-Data Transfer Timing
16.4.135 Measurement accuracy
after
μController-based
calibration
T
J
-15
–
15
°C-40 °C < T
J < 150 °C
16.4.136 Settling time
Tset
––
30
μs
4) after measurement
mode change; CSN “high”
to settled output voltage at
interconnect
V
A
1) Not subject to production test, specified by design.
2) normal operation continuous current should not exceed 300mA (for each low-side LS1 and LS2)
3) Production testing in 20 kbit/s mode
4)
Tested on wafer level only.
Table 14
Electrical Characteristics (cont’d)
V
S = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
0
+
1 2 3 4 5 6 7 8 9 10
15
1
+
0
-
1
-
2
-
0
3
-
4
-
5
-
6
-
11
-
12
-
13
-
14
-
7
-
8
-
9
-
10
-
15
-
FI
-
CSN high to low: DO is enabled. Status information transferred to output shift register
CSN low to high: data from shift register is transferred to output functions
DI: will accept data on the falling edge of CLK signal
DO: will change state on the rising edge of CLK signal
Previous status
11 12 13 14
1
Actual data
New data
Actual status
Actual data
Old data
e.g. HS switch
DO
DI
CSN
CLK
time
FO
-
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