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參數資料
| 型號： | TLV320A11IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 4/55頁 |
| 文件大小： | 263K |
| 代理商： | TLV320A11IPFBG4 |
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1–6
1.6
Definitions and Terminology
Data transfer interval
The time during which data is transferred from DOUT to DIN. The interval is 16 shift clocks
and the data transfer is initiated by the falling edge of the FS signal.
Signal data
This refers to the input signal and all of the converted representations through the ADC
channel, and the signal through the DAC channel to the analog output. This is in contrast
with the purely-digital software control data.
Primary
communication
Primary communication refers to the digital data-transfer interval. Since the device is syn-
chronous, the signal data words from the ADC channel and to the DAC channel occur si-
multaneously.
Secondary
communication
Secondary communication refers to the digital control and configuration data-transfer in-
terval into DIN, and the register read-data cycle from DOUT. The data transfer occurs when
requested by hardware or software.
SPI
Serial peripheral interface
Frame/pulse sync
Frame/pulse sync refers only to the falling edge of the signal FS that initiates the data-
transfer interval. The primary FS starts the primary communication, and the secondary FS
starts the secondary communication.
Frame/pulse sync and
sampling period
Frame/pulse sync and sampling period is the time between falling edges of successive pri-
mary FS signals and it is always equal to 256xSCLK if the number of cascading devices is
less than 5, or 512 xSCLK if the number of cascading devices is greater than 4.
fs
The sampling frequency
ADC channel
ADC channel refers to all signal-processing circuits between the analog input and the
digital conversion result at DOUT.
DAC channel
DAC channel refers to all signal-processing circuits between the digital data word applied
to DIN and the differential output analog signal available at OUTP and OUTM.
Host
A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.
Dxx
Bit position in the primary data word (xx is the bit number).
DSxx
Bit position in the secondary data word (xx is the bit number).
d
The alpha character d represents valid programmed or default data in the control-register
format (see Section 3.2, Secondary Serial Communication) when discussing other data bit
portions of the register.
PGA
Programmable gain amplifier
FIR
Finite-duration impulse response
DCSI
Direct configuration serial interface for host control
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| TLV320A20KIPFBRG4 | 功能描述:接口—CODEC 3.3-V 12-Bit Univ Bus Driver RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320A23BIRHDRG4 | 功能描述:接口—CODEC 20-Bit Buffer/Driver With 3-State Outputs RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320A24KIPFBRG4 | 功能描述:接口—CODEC 18-Bit Buffer/Driver With 3-State Outputs RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320A3204IRHBRG4 | 功能描述:接口—CODEC Very Low-Pwr Stereo Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320A3254IRHBRG4 | 功能描述:接口—CODEC Very Low-Pwr Stereo Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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