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參數資料
型號: TLV320A11IPFBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: GREEN, PLASTIC, TQFP-48
文件頁數: 44/55頁
文件大小: 263K
代理商: TLV320A11IPFBG4
A–1
Appendix A
Register Set
Bits D15 through D13 represent the device address in the cascade set by the automatic cascade detection described
in Section 2.1.13. In cascading, the master is the device directly connected to the DSP. For example, if there are four
devices in the cascade, as shown in row 4 of Table A-1 and in Section 2.7.5, the device address D15-D13 of the master
will have a binary value of 011. The other three slaves’ addresses are 010, 001, and 000, corresponding to their
positions in the cascade. The device address for a stand-alone device is always 000. Bits D11 through D8 comprise
the address of the register that is written with data carried in D7 through D0. D12 determines a read or write cycle
to the addressed register; a low selects a write cycle.
The following table shows the register map.
REGISTER MAP
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Device Address
RW
Register Address
X
Control Register Content
Table A–1. Device Address
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
Device Address R/W Register Adress
X
Register Content
Device 0
REGISTER MAP
000
Device 1
001
Device 2
010
Device 3
011
Device 4
100
Device 5
101
Device 6
110
Device 7
111
8
7
6
5
4
3
1
2
DEVICE ADDRESS (D15–D13)
# Devices
in Cascade
Table A–2. Register Address
REGISTER NO.
D11
D10
D9
REGISTER NAME
0
No operation
1
0
1
Control 1
2
0
1
0
Control 2
3
0
1
Control 3
4
1
0
Control 4
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