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參數(shù)資料
| 型號： | TLV320A11IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 7/55頁 |
| 文件大小： | 263K |
| 代理商： | TLV320A11IPFBG4 |
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2–1
2 Functional Description
2.1
Device Functions
2.1.1
Operating Frequencies
The sampling frequency represented by the frequency of the primary communication is derived from the master clock
(MCLK) input with the following equation:
Fs = Sampling (conversion) frequency = MCLK/(256
× N), N = 1, 2..., 32
The inverse of the sampling frequency is the time between the falling edges of two successive primary frame-sync
signals. This time is the conversion period. For example, to set the conversion rate to 8 kHz, MCLK = 256
× N × 8000.
NOTE:The value of N is defined in control register 2 and its power-up value is 32.
2.1.2
ADC Signal Channel
Both IN (INP, INM) and AUX (AURXFP, AURXM) inputs can use the built-in antialiasing filter that can be bypassed
by writing a 1 to bit D5 of control register 1. The AUX input can also be connected to the general-purpose amplifier
A1 for general-purpose applications, such as electret-microphone interface and 2-to-4-wire hybrid interface, by
writing a 1 to bit D6 of control register 1. Bit D4 of control register 1 selects between IN or AUX for the ADC. The
selected input signal is amplified by the PGA and applied to the ADC input. The ADC converts the signal into
discrete-output digital words in 2s-complement data format, corresponding to the analog-signal value at sampling
time. These 16-bit (or 15-bit) digital words, representing sampled values of the analog input signal after PGA, are
clocked out of the serial port (DOUT) at the positive edge of SCLK during the frame-sync (FS) interval at the rate of
one bit for each SCLK and one word for each primary communication. During secondary communication, the data
previously programmed into the registers can be read out. If a register read is not required, all 16 bits are cleared to
0 in the secondary communication. This read operation is accomplished by sending the appropriate register address
(D11-D9) with the read bit (D12) set to 1 during present secondary communication. The timing sequence is shown
in Figures 2–1 and 2–2.
The decimation FIR filter can be bypassed by writing a 1 to bit D2 of control register 1. The whole ADC channel can
be turned off for power savings by writing 01 to bits D2 and D1 of control register 3.
D0
16 SCLKs
SCLK
FS
DOUT
(16-bit)
DOUT
(15+1-bit)
D1
MSB
LSB
D15
M/S
D1
0
1
15
16
MSB
D15
D14
……
NOTES: A. M/S is used to indicate whether the 15-bit data comes from a master or a slave device (master: M/S=1, slave: M/S=0).
B. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edging of SCLK number 0; the last bit (D0,M/S)
is stable at the falling edging of SCLK number 15.
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