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| 型號(hào)： | TLV320ADC3001IYZHR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁(yè)數(shù)： | 10/81頁(yè) |
| 文件大小： | 836K |
| 代理商： | TLV320ADC3001IYZHR |
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LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
RD (n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Right-Channel Data
2
1
0
3
2
1
0
3
n-3
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
2
1
0
LD(n)
LD(n+1)
3
2
1
0
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Ch_Offset_1 = 1
LD (n)
LD(n+1)
RD (n)
2
1
0
3
2
1
0
3
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Ch_Offset_1 = 0
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
Figure 17. Left-Justified Mode (Standard Timing)
Figure 18 shows the left-justified mode with Ch_Offset_1 = 1.
Figure 18. Left-Justified Mode With Ch_Offset_1 = 1
Figure 19 shows the left-justified mode with Ch_Offset_1 = 0 and bit clock inverted.
Figure 19. Left-Justified Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For left-justified mode, the number of bit clocks per frame should be greater than twice the programmed word
length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by
at least the programmed word length of the data.
When the time-slot-based channel assignment is disabled (page 0 / register 38, bit D0 = 0), the left and right
channels have the same offset Ch_Offset_1 (page 0 / register 28), and each edge of the word clock starts data
transfer for one of the two channels, depending on whether or not channel swapping is enabled. Data bits are
18
Copyright
2008–2011, Texas Instruments Incorporated
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