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參數資料
| 型號： | TLV320ADC3001IYZHR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁數： | 25/81頁 |
| 文件大小： | 836K |
| 代理商： | TLV320ADC3001IYZHR |
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SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for
them to charge up suddenly when the input is changed from being unselected to selected for connection to an
ADC PGA. This option is controlled in page 1 / register 52 through page 1 / register 57. The user should specify
this option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input
bypass path, because it can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320ADC3001 should be ac-coupled to analog input sources, the
only exception to this generally being if an ADC is being used for dc voltage measurement. The ac-coupling
capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 35 k
with an input level control setting of 0
dB, and 62.5 k
when the input level control is set at –6 dB. For example, using a 0.1-μF ac-coupling capacitor
at an analog input will result in a high-pass filter pole of 45.5 Hz when the 0-dB input level-control setting is
selected. To set a high-pass corner for the application, the following input impedance table (Table 5) has been
provided with various mixer gains and microphone PGA ranges.
Table 5. Single-Ended Input Impedance vs PGA Ranges (1)
Mixer Gain (dB)
Microphone PGA Range (dB)
Input Impedance (
Ω)
0
–5.5
35,000
0
6
–11.5
38,889
0
12
–17.5
42,000
0
18
–23.5
44,074
0
24
–29.5
45,294
0
30
–35.5
45,960
0
36
–40
46,308
–6
0
–5.5
62,222
–6
6
–11.5
70,000
–6
12
–17.5
77,778
–6
18
–23.5
84,000
–6
24
–29.5
88,148
–6
30
–35.5
90,588
–6
36
–40
91,919
(1)
Valid when only one input is enabled
MICBIAS GENERATION
The TLV320ADC3001 includes a programmable microphone bias output voltage (MICBIAS), capable of providing
output voltages of 2 V or 2.5 V (both derived from the on-chip band-gap voltage) with 4-mA output-current drive
capability. In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip
switch, or it can be powered down completely when not needed, for power savings. This function is controlled by
register programming in page 1 / register 51.
ADC Decimation Filtering and Signal Processing
The TLV320ADC3001 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high dynamic range.
The decimation filter can be chosen from three different types, depending on the required frequency response,
group delay, and sampling rate.
Processing Blocks
The TLV320ADC3001 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
Copyright
2008–2011, Texas Instruments Incorporated
31
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