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參數資料
| 型號： | TLV320ADC3001IYZHR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁數： | 11/81頁 |
| 文件大小： | 836K |
| 代理商： | TLV320ADC3001IYZHR |
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RD(n)
RD(n+1)
2
1
0
3
2
1
0
3
LD(n)
RIGHT CHANNEL
LEFT CHANNEL
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Ch_Offset_1 = 1
LD (n)
LD(n+1)
2
1
0
3
2
1
0
3
RD (n)
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Left Channel
Right Channel
Ch_Offset_1 = 0
Ch_Offset_2 = 1
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
valid on the rising edges of the bit clock. With the time-slot-based channel assignment enabled (page 0 / register
38, bit D0 = 1), the left and right channels have independent offsets (Ch_Offset_1 and Ch_Offset_2). The rising
edge of the word clock starts data transfer for the first channel after a delay of its programmed offset
(Ch_Offset_1) for this channel. Data transfer for the second channel starts after a delay of its programmed offset
(Ch_Offset_2) from the LSB of the first-channel data. The falling edge of the word clock is not used.
With no channel swapping, the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit
clock following the rising edge of the word clock. And, the MSB of the right channel is valid on the (Ch_Offset_1
+ 1)th rising edge of the bit clock following the falling edge of the word clock. The operation in this case, with
offset of 1, is shown in the timing diagram of Figure 18. Because channel swapping is not enabled, the
left-channel data is before the right-channel data. With channel swapping enabled, the MSB of the right channel
is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And,
the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the falling
edge of the word clock. The operation in this case, with offset of 1, is shown in the timing diagram of Figure 20.
As shown in the diagram, the right-channel data of a frame is before the left-channel data of that frame, due to
channel swapping. Otherwise, the behavior is similar to the case where channel swapping is disabled. The MSB
of the right-channel data is valid on the second rising edge of the bit clock after the rising edge of the word clock,
due to an offset of 1. Similarly, the MSB of the left-channel data is valid on the second rising edge of the bit clock
after the falling edge of the word clock.
Figure 20. Left-Justified Mode With Ch_Offset_1 = 1, Channel Swapping Enabled
When time-slot-based mode is enabled with no channel swapping, the MSB of the left channel is valid on the
(Offset1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the MSB of the right
channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the left channel.
Figure 21 shows the operation with time-slot-based mode enabled and Ch_Offset_1 = 0 and Ch_Offset_2 = 1.
The MSB of the left channel is valid on the first rising edge of the bit clock after the rising edge of the word clock.
Data transfer for the right channel does not wait for the falling edge of the word clock, and the MSB of the right
channel is valid on the second rising edge of the bit clock after the LSB of the left channel.
Figure 21. Left-Justified Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1
For the case with time-slot-based mode enabled and channel swapping enabled, the MSB of the right channel is
valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And, the
Copyright
2008–2011, Texas Instruments Incorporated
19
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