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參數資料
| 型號： | TLV320ADC3001IYZHR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封裝： | GREEN, DSBGA-16 |
| 文件頁數： | 8/81頁 |
| 文件大?。?/td> | 836K |
| 代理商： | TLV320ADC3001IYZHR |
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3
N
WCLK
BCLK
DOUT
N -1
N -2
N -
0
1
N -2
-3
2
1
0
X
N -1
X
1/fs
DOUT_Tristate
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
The audio serial interface on the TLV320ADC3001 has an extensive I/O control to allow for communicating with
two independent processors for audio data. The processors can communicate with the device one at a time. This
feature is enabled by register programming of the various pin selections.
The audio bus of the TLV320ADC3001 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 /
register 27, bits D5
–D4. In addition, the word clock and bit clock can be independently configured in either
master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define
the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of
this clock corresponds to the maximum of the selected ADC sampling frequencies.
The bit clock is used to clock in and out the digital audio data across the serial bus. When in master mode, this
signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 /
register 30 (see Figure 31). Accommodating various word lengths as well as supporting the case when multiple
TLV320ADC3001s share the same audio bus may require that the number of bit-clock pulses in a frame be
adjusted.
The TLV320ADC3001 also includes a feature to offset the position of the start of data a transfer with respect to
the word clock. There are two configurations that allow the user to use either a single offset for both channels or
to use separate offsets. Ch_Offset_1 reference represents the value in page 0 / register 28, and Ch_Offset_2
represents the value in page 0 / register 37. When page 0 / register 38, bit D0 is set to zero (time-slot-based
channel assigment is disabled), the offset of both channels is controlled, in terms of number of bit clocks, by the
programming in page 0 / register 28 (Ch_Offset_1). When page 0 / register 38, bit D0 = 1 (time-slot-based
channel assignment enabled), the first channel is controlled, in terms of number of bit clocks, by the
programming in page 0 / register 28 (Ch_Offset_1), and the second channel is controlled, in terms of number of
bit clocks, by the programming in page 0 / register 37 (Ch_Offset_2), where register 37 programs the delay
between the first word and the second word. Also, the relative order of the two channels can be swapped,
depending on the programmable register bit (page 0 / register 38, bit D4) that enables swapping of the channels.
The TLV320ADC3001 also supports a feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the mode
of audio interface chosen. This can be configured by writing to page 0 / register 29, bit D3.
The TLV320ADC3001 further includes programmability (page 0 / register 27, bit D0) to place DOUT in the
high-impedance state at the end of data transfer (i.e., at the end of the bit cycle corresponding to the LSB of a
channel). By combining this capability with the ability to program at what bit clock in a frame the audio data
begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple ADCs able to use a single
audio serial data bus. To further enhance the 3-state capability, the TLV320ADC3001 can be put in a
high-impedance state half of a bit cycle earlier by setting page 0 / register 38, bit D1 to 1. When the audio serial
data bus is powered down while configured in master mode, the pins associated with the interface are put into a
high-impedance output state.
Figure 14. Both Channels Enabled, Early Hi-Z State Enabled
Either or both of the two channels can be disabled in LJF, I2S, and DSP modes by using page 0 / register 38,
bits D3
–D2. Figure 14 shows the interface timing when both channels are enabled and early Hi-Z state is
enabled. Figure 15 shows the effect of setting page 0 / register 38, bit D2, first channel disabled, and setting
page 0 / register 27, bit D0 to 1, which enables placing DOUT in the high-impedance state. If placing DOUT in
the high-impedance state is disabled, then the DOUT signal is driven to logic level 0.
16
Copyright
2008–2011, Texas Instruments Incorporated
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