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參數資料
| 型號： | TLV320ADC3101IRGER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封裝： | GREEN, PLASTIC, VQFN-24 |
| 文件頁數： | 11/84頁 |
| 文件大?。?/td> | 1363K |
| 代理商： | TLV320ADC3101IRGER |
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LD (n)
LD(n+1)
RD (n)
2
1
0
3
2
1
0
3
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Ch_Offset_1 = 0
RD(n)
RD(n+1)
2
1
0
3
2
1
0
3
LD(n)
RIGHT CHANNEL
LEFT CHANNEL
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3
Ch_Offset_1 = 1
www.ti.com...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Figure 19 shows the left-justified mode with Ch_Offset_1 = 0 and bit clock inverted.
Figure 19. Left-Justified Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For left-justified mode, the number of bit clocks per frame should be greater than twice the programmed word
length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by
at least the programmed word length of the data.
When the time-slot-based channel assignment is disabled (page 0 / register 38, bit D0 = 0), the left and right
channels have the same offset Ch_Offset_1 (page 0 / register 28), and each edge of the word clock starts data
transfer for one of the two channels, depending on whether or not channel swapping is enabled. Data bits are
valid on the rising edges of the bit clock. With the time-slot-based channel assignment enabled (page 0 / register
38, bit D0 = 1), the left and right channels have independent offsets (Ch_Offset_1 and Ch_Offset_2). The rising
edge of the word clock starts data transfer for the first channel after a delay of its programmed offset
(Ch_Offset_1) for this channel. Data transfer for the second channel starts after a delay of its programmed offset
(Ch_Offset_2) from the LSB of the first-channel data. The falling edge of the word clock is not used.
With no channel swapping, the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit
clock following the rising edge of the word clock. And, the MSB of the right channel is valid on the (Ch_Offset_1
+ 1)th rising edge of the bit clock following the falling edge of the word clock. The operation in this case, with
offset of 1, is shown in the timing diagram of Figure 18. Because channel swapping is not enabled, the
left-channel data is before the right-channel data. With channel swapping enabled, the MSB of the right channel
is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. And,
the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the falling
edge of the word clock. The operation in this case, with offset of 1, is shown in the timing diagram of Figure 20.
As shown in the diagram, right-channel data of a frame is before that frame’s left-channel data, due to channel
swapping. Otherwise, the behavior is similar to the case where channel swapping is disabled. The MSB of the
right-channel data is valid on the second rising edge of the bit clock after the rising edge of the word clock, due
to an offset of 1. Similarly, the MSB of the left-channel data is valid on the second rising edge of the bit clock
after the falling edge of the word clock.
Figure 20. Left-Justified Mode With Ch_Offset_1 = 1, Channel Swapping Enabled
Copyright 2008–2009, Texas Instruments Incorporated
19
Product Folder Link(s) :TLV320ADC3101
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