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參數資料
| 型號： | TLV320ADC3101IRGER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封裝： | GREEN, PLASTIC, VQFN-24 |
| 文件頁數： | 8/84頁 |
| 文件大小： | 1363K |
| 代理商： | TLV320ADC3101IRGER |
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DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
8-bit Register Data
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
DA(6)
DA(0)
RA(7)
RA(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
SDA
SCL
DA(6)
DA(0)
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
D(7)
D(0)
8-bit Register Data
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
Figure 12. I2C Write
Figure 13. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental
register.
Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmits for the
next eight clocks the data of the next incremental register.
DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between the host processor and the TLV320ADC3101 via the digital-audio serial-data
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options,
support for I2S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation,
flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices
within a system directly.
The audio serial interface on the TLV320ADC3101 has an extensive I/O control to allow for communicating with
two independent processors for audio data. The processors can communicate with the device one at a time. This
feature is enabled by register programming of the various pin selections.
The audio bus of the TLV320ADC3101 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 /
register 27, bits D5–D4. In addition, the word clock and bit clock can be independently configured in either
master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define
the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of
this clock corresponds to the maximum of the selected ADC sampling frequencies.
The bit clock is used to clock in and out the digital audio data across the serial bus. When in master mode, this
signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 /
register 30 (see Figure 31). Accommodating various word lengths as well as supporting the case when multiple
TLV320ADC3101s share the same audio bus may require that the number of bit-clock pulses in a frame be
adjusted.
16
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TLV320ADC3101
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