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參數資料
| 型號： | TLV5621IDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 75 us SETTLING TIME, 8-BIT DAC, PDSO14 |
| 封裝： | GREEN, PLASTIC, SOIC-14 |
| 文件頁數： | 13/19頁 |
| 文件大?。?/td> | 321K |
| 代理商： | TLV5621IDRG4 |
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times one
or times two gain.
On power-up, the DACs are reset to CODE 0.
Each output voltage is given by:
V
O
(DACA|B|C|D)
+ REF
CODE
256
(1
) RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.
Table 1. Ideal-Output Transfer
D7
D6
D5
D4
D3
D2
D1
D0
OUTPUT VOLTAGE
0
GND
0
0000001
(1/256)
× REF (1+RNG)
0
1111111
(127/256)
× REF (1+RNG)
1
0000000
(128/256)
× REF (1+RNG)
1
(255/256)
× REF (1+RNG)
data interface
The data interface has two modes of operation; single and double buffered. Both modes serially clock in bits
of data using DATA and CLK whenever EN is high. When EN is low, CLK is disabled and data cannot be loaded
into the buffers.
In the single buffered mode, the DAC outputs are updated on the last/twelfth falling edge of CLK, so this mode
only requires a two-wire interface with EN tied high (see Figure 1 and Figure 2).
In the double buffered mode (startup default), the outputs of the DACs are updated on the falling edge of the
EN strobe (see Figure 3 and Figure 4). This allows multiple devices to share data and clock lines by having only
separate EN lines.
single-buffer mode (MODE = 1)
When a two wire interface is used, EN is tied high and the input to the device is always active; therefore, random
data can be clocked into the input latch. In order to regain word synchronization, twelve zeros are clocked in
as shown in Figure 1, and then a data or control word is clocked in. In Figure 1, the MODE bit is set to one, and
a control word is clocked in with the DAC outputs becoming active after the last falling edge of the control word.
Figure 2 shows valid data being written to a DAC, note that CLK is held low while the data is invalid. Data can
be written to all four DACs and then the control word is clocked in which sets the MODE bit to 1. At the end of
the control word, the data is latched to the inputs of the DACs.
Note that once the MODE bit has been set, it is not possible to clear it, i.e., it is not possible to move from single
to double-buffered mode.
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